From: Nanoscale cryptography: opportunities and challenges
Circuit
Hybrid CMOS/NanoDevice FPGA
FCMOS = 45 nm, Fnano = 4.5 nm, Max fan in = 7
Static power consumption (mW)
Dyanamic power consumption (mW)
Round function
0.7
16
Round operation
6.5
19
Final round addition
2.7
Round word computation
0.9