Fig. 1
From: Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process
a–h Schematic of the fabrication process of the DNTT TFT based on the photolithography process. Photographs of the DNTT TFT fabricated via (i) photolithography and (j) shadow mask method, where W/L = 12 μm /6 μm and 200 μm /100 μm, respectively. Scale bars are 20 μm (i) and 200 μm (f). (k) ID–VG curves of DNTT TFTs developed using different fabrication methods for VD =  − 2 V. (l) Comparison of currents, field-effect mobility, and threshold voltage of the fabricated devices