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Figure 4 | Nano Convergence

Figure 4

From: Interface engineering for high performance graphene electronic devices

Figure 4

Passivation of target substrate for transferred graphene. a, Field effect measurement at T = 293 K for graphene on HMDS (black) and for graphene on bare SiO2 (red). Reproduced with permission [73]. Copyright 2010, American Chemical Society. b, Histogram of mobility and the Dirac point of different graphene FETs on bare SiO2/Si and on OTMS-modified SiO2/Si substrates at room temperature under ambient conditions. Reproduced with permission [77]. Copyright 2011, John Wiley and Sons. c, Transfer characteristics (Ids-Vg) for a typical parylene gated FET in air, baked at 400 K in vacuum, and in air 30 min after baking (top panel). Drain-source current versus back-gate voltage for silicon oxide devices in air, baked at 400 K in vacuum, and in air 30 min after baking (bottom panel). Reproduced with permission [78]. Copyright 2009, AIP Publishing LLC. d, The change in carrier density in graphene on different surface (fluoropolymer and SiO2) with elapse of time in an air ambient. Reproduced with permission [79]. Copyright 2011, AIP Publishing LLC.

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