Figure 6
From: Interface engineering for high performance graphene electronic devices
Seeding ALD of high-k dielectric on graphene. a, Schematic diagram showing top-gate graphene FET structure with PVP-seeded Al2O3 gate dielectric. Reproduced with permission [125]. Copyright 2012, AIP Publishing LLC. b, Transfer characteristics (Id-Vg) of top-gate graphene FET before (black square) and after (red circle) the graphene channel is deposited with PVP. Inset: transconductance of the graphene FETs with different gate dielectrics as a function of gate voltage. Reproduced with permission [125]. Copyright 2012, AIP Publishing LLC. c, The time-dependent VDirac shift of graphene FET before (black square) and after (red circle) the graphene channel is deposited with PVP. Reproduced with permission [125]. Copyright 2012, AIP Publishing LLC. d, Output characteristics (Id-Vd) of transistors based on CVD monolayer graphene with 9nm Al2O3 (red line) and 24 nm heterogeneous integrated dielectrics (dashed blue line) via different depositing methods. Reproduced with permission [128]. Copyright 2011, IEEE. e, Schematic diagram presenting the functionalized graphene-seeded Al2O3 stack on graphene. Reproduced with permission [129]. Copyright 2013, American Chemical Society. f, Surface morphology of the Al2O3 films deposited on graphene (top) and functionalized graphene (bottom). Scan size: 1 × 1 μm2. Reproduced with permission [129]. Copyright 2013, American Chemical Society. g, Leakage current densities (at +3 MV/cm2) versus EOT for dielectrics with functionalized graphene seed layer (red triangle) and Al seed layer (black square) on graphene. Reproduced with permission [129]. Copyright 2013, American Chemical Society.