Nano Convergence

Table 1 Performance results for SHA-512 building blocks mapped on CMOS FPGA

From: Nanoscale cryptography: opportunities and challenges

Circuit	CMOS FPGA
	F_CMOS = 45 nm
	Depth	LUT	Linear size	Area (μm ²)	Delay (ns)
Round function	1	1218	8 × 8	124538	6.7
Round operation	67	2769	27 × 27	304722	39.7
Final round addition	19	286	9 × 9	36320	22
Round word computation	7	1440	20 × 20	151369	3.7

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