Nano Convergence

Table 2 Performance Results For SHA-512 Building blocks mapped on two-cell hybrid CMOS-NANO FPGA fabric

From: Nanoscale cryptography: opportunities and challenges

Circuit	Hybrid CMOS/NanoDevice FPGA
	F_CMOS = 45 nm, F_nano = 4.5 nm, Max fan in = 7
	Depth	Tile size	No. of nano devices	Area (μm²)	Delay
Round function	23	12 × 12	2309	299	1.76
Round operation	111	25 × 25	5786	1296	14.2
Final round addition	67	7 × 7	602	168	10.6
Round word computation	14	23 × 23	2146	1096	1.6

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