Table 3 Performance results for SHA-512 building blocks mapped on two-cell hybrid CMOS-NANO FPGA with two different defect rates
Circuit | No defect | 10 % defective cells | 30 % defective cells | |||
|---|---|---|---|---|---|---|
Area | Delay (ns) | Area (μm 2) | Delay (ns) | Area (μm 2) | Delay (ns) | |
Round function | 299 | 1.76 | 351 | 1.76 | 407 | 1.79 |
Round operation | 1296 | 14.2 | 1512 | 15.68 | 2540 | 17.24 |
Final round addition | 102 | 10.56 | 102 | 10.56 | 168 | 10.6 |
Round word computation | 1096 | 1.6 | 1096 | 1.8 | 1195 | 1.92 |