Nanoscale cryptography: opportunities and challenges

Nano Convergence

Table 4 Power consumption of SHA-512 building blocks mapped on two-cell hybrid CMOS-NANO FPGA

Circuit	Hybrid CMOS/NanoDevice FPGA
	F_CMOS = 45 nm, F_nano = 4.5 nm, Max fan in = 7
	Static power consumption (mW)	Dyanamic power consumption (mW)
Round function	0.7	16
Round operation	6.5	19
Final round addition	0.7	2.7
Round word computation	0.9	16