Fig. 2

a Optical image of memristors integrated on top of CMOS circuitry [34]. b Process flow for the fabrication of etched bit cells by nanoimprint lithography consisting of 6 steps: 1 bottom electrode and functional layers consisting of memristor and/or selector materials are deposited. 2 Bits are patterned by nanoimprint lithography. 3 Etch mask is deposited in a lift off process. 4 Bits are created by etching through the active layers. 5 A planarization layer is deposited which also serves as an interlayer dielectric (ILD) which is etched back to expose the bits. 6 Top electrodes are patterned by photolithography. c SEM image of a 30 nm memristor bit fabricated by the process defined in b