Fig. 3From: Accurate extraction of WSe2 FETs parameters by using pulsed I-V method at various temperaturesExplanation of the measurement methods for (a) DC and (b) PIV methods. The insert in a explains the step width at each bias step (t sw). The t on, t off, and V base in the inset of b are 10−4 s, 1 s, and 0 V, respectively. In PIV, the drain bias is synchronized with the gate biasBack to article page