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Nano Convergence

Table 2 The device dimensions of baseline FDSOI device/FinFET vs. the hysteresis of FE-FDSOI/FE-FinFET

From: Study of a hysteresis window of FinFET and fully-depleted silicon-on-insulator (FDSOI) MOSFET with ferroelectric capacitor

Gate length × width (nm × nm)

Forward VFerroelectric (V)

Reverse VFerroelectric (V)

Hysteresis (V)

FE-FDSOI

 1000 × 80

1.14

− 0.35

1.49

 1000 × 85

1.35

− 0.45

1.80

 1000 × 105

1.38

− 0.67

2.05

FE-FinFET

 180 × 20

0.50

− 0.48

0.98

 180 × 250

1.36

− 0.98

2.34

 5000 × 20

1.79

− 1.14

2.93

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