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Fig. 4 | Nano Convergence

Fig. 4

From: High-performance printed electronics based on inorganic semiconducting nano to chip scale structures

Fig. 4

adapted from [59]. b Schematic diagram illustrates stages of the Si NRs fabrication and selective doping (i) The source wafer consists a layer of active Si < 100 > with 70 nm thick, on top of 2 µm of BOX, supported by 600 µm bulk Si. (ii) Si NR’s geometry is defined by conventional UV lithography procedure. UV lithography is performed by spin coating photoresist, followed by soft baking, the samples are exposed to UV source and subsequentially the NRs definition are developed. (iii) Dry etching is performed in this step by reactive ion etching (RIE) using a combination of CH3/O2 gas sources, to finalize the structure of NRs structure after photoresist removal using acetone and IPA. (iv) The first step to perform a selective n + type doping of active regions (source/drain for FETs) is by applying plasma enhanced chemical vapour deposition (PECVD) of SiOx layer. (v) The SiOx barriers over the active regions are etched away by dry etching. (vi) Spin on dopant method of phosphorus is used to create ohmic contacts at source and drain regions on the source wafer while the channel is masked by SiOx, served as a barrier. A wet etching method using hydrofluoric acid is performed to remove both dopant diffusion barrier layer and buried oxide layer leading in release of the NRs from the bulk wafer, allowing the selectively doped NRs to be transfer printed to any flexible substrate. Adapted with permission from [46]. c Schematic illustration of the fabrication of NWs/NMs by use of anisotropic wet-chemical etching techniques applied to bulk wafers

Schematic representation of the growth of nano scale structures via top-down methods. a Silicon nanowires using metal assisted chemical etching (MACE) process. Schematics

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