Fig. 7

a–p The process flow of fabrication and transfer of UTCs on to the flexible polyimide substrate through backside chemical etching and PDMS assisted-wafer scale transfer process, respectively. Reprinted with permission from Ref [26]. Copyright (2018) WILEY. a Schematic illustration of integrated multilateral stack on flexible substrate. Schematic illustration of backside etching of bulk wafer to UTCs with (b) initial bulk wafer, (c) back side of UTCs membrane with selective thermal oxide hard mask, and (d) the front side. Transfer printing process with two stages: “Stage 1” transferring to carrier substrate with schematic illustration of (e) PDMS spin-coated temporary second wafer, (f) attaching the UTCs to PDMS, and (g) lacer cutting to remove the bulk silicon; “Stage 2” transferring to receiver substrate with schematic illustration of (h) polyimide spin-coated on temporary third wafer, (i) transfer the UTCs on top of polyimide, (j) chemical etching of PDMS and remove the second temporary wafer to expose the top surface, (k) spin-coating polyimide to encapsulate the UTCs and (l) releasing the temporary third wafer to obtain encapsulated UTCs. m Digital image of flexible UTCs transferred on polyimide and (n) cross sectional SEM image of UTCs. The photographic image of (o) flexible UTCs and (p) the n-MOSFET device encapsulated by polyimide