Fig. 9
From: High-performance printed electronics based on inorganic semiconducting nano to chip scale structures
a SEM image of a representative NR-FET with the source (S), drain (D), and gate (G) electrodes labelled in it comprising of ten NRs as active layer. b Photograph of flexible NR-FETs on PI substrate wrapped on a curved surface. c Transfer characteristics (experimental (line) versus model (dashed) simulations) and (d) output characteristics of the NR-FET at planar, tensile, and compressive bending conditions (Rc = 40 mm). e Variation of the drain current at planar condition after cycles of compressive and tensile bending at VDS = VGS = 4 V. f Gate dielectric leakage current Vs gate voltage after subjecting it to cyclic bending. g Breakdown voltage characteristics of four randomly chosen devices after subjecting to cyclic bending of 100 cycles. Reproduced with permission from [46]