Fig. 12

Applications of high-performance hafnia ferroelectrics. Schematic of a technology node on DRAM (dynamic random-access memory) capacitor (SIS: silicon–insulator–silicon MIS: metal–insulator–silicon, MIM: metal–insulator–metal) and b pillar-structured capacitor (F: minimum feature size). c Gate leakage current density versus physical thickness with various material and structures (Z: ZrO₂, S: Sr, T: TiO₂, H: HfO₂ A: Al₂O₃, ATO: Al doped TiO₂). d Device structure of FinFET and e TCAD simulation result for FinFET. f Schematic of HZO-AlN ultra sonic transducer. Figure 12 were redrawn from Ref. [13, 43, 64]