Fig. 2
From: Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process
a Schematic of the device structure. b Electrical characteristics of the DNTT TFT with various thicknesses of the first PMMA layer for VD =  − 2 V. c Schematic of the device structure.d Electrical characteristics of the DNTT/SL device with various thickness of the second PMMA layer for VD =  − 2 V, where the thickness of the first PMMA is 20 nm