Fig. 3
From: Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process
a Schematic of the DNTT ternary logic device structure. b Cross-sectional TEM image of the stack-channel ternary logic device and EDS analysis of the device for c Al and d S. Scale bar = 20 nm. e ID–VG curve and differential conductance (gm) of the DNTT ternary logic device for VD =  − 2 V. f ID–VG curve of the device with a linear scale for VD =  − 2 V. Vth for I1 and I2 (Vth1 and Vth2, respectively) are defined on the linear scale transfer curve via the linear extrapolation method. g ID–VG curve of the device for VD =  − 1 to − 5 V in − 1 V steps. h Cross-sectional schematic of the device structure of the DNTT ternary logic device with various resistance components