Fig. 4
From: Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process
a Statistics of the current level of each state as I2 (on state), I1 (intermediate state), and I0 (off state). b Histograms of the threshold voltages and subthreshold swings of 25 separate DNTT ternary logic devices for VD = − 2 V. c Electrical characteristics of the DNTT ternary logic device intermittently measured for an extended period of over 120 days to investigate long-term stability for VD =  − 2 V. d VTCs of the ternary logic inverter for VDD = 1–6 V. Inset: schematic of a resistive-load ternary logic inverter. e Voltage gains of the two-state transition for VDD = 5 V. f Voltage gains versus VDD