Fig. 3

Illustration of system-level RS networks with a 1T1R configuration, which almost all systems demonstrations used. a Schematic to illustrate the configuration. At each intersection of one word line with the two perpendicular lines (bit line and source line), a synaptic/memory cell comprises a selector transistor and a RS element. b Example of an experimental demonstration, reproduced with permission from [28]. It is clear that the chip contains a considerable amount of peripheral circuitry besides the actual RS network