Fig. 7
From: Multi-level resistive switching in hafnium-oxide-based devices for neuromorphic computing
Illustrations of implementing ferroelectric switching. a Top: Schematic of a FE transistor (FeFET) with different domain orientations (arrows in boxes) in the gate oxide. S—source, G—gate, D—drain. Ferroelectric switching in the gate oxide will cause a shift of the transistor threshold voltage VT, creating a memory window in the transistor transfer characteristics (bottom). Whether in a three- or two-terminal device, gradual switching of different domains in a FE film can lead to multi-level states if exploited accordingly. b Schematic band diagrams of Schottky-to-ohmic transition device. Depending on the FE orientation, illustrated by the arrows in boxes, the contact between the FE oxide and an adjacent electrode (with an appropriate work function) can be a Schottky contact (red, increased barrier) or an ohmic contact (blue, reduced barrier), leading to a high and a low resistance state, respectively. c Schematic band diagrams of a FE tunnel junction. Depending on the FE orientation, electronic carriers can be accumulated (blue, band bending downwards) or depleted (red, band bending upwards) at the interface, leading to a lower or a higher resistance state due to increased/decreased tunnelling through the FE oxide from accumulated/depleted carriers at the interface. EC conduction band energy, EF Fermi level energy. Note that the effect of FES on the insulator was disregarded in this schematic. d Circuit diagram of a DRAM configuration, where the standard dielectric capacitor was replaced by a variable FE capacitor. WL—word line, BL—bit line