Fig. 9

ECRAM array implementation. a Schematic of an ECRAM array comprising three metal lines for source, drain, and gate. b Optical microscope image of 5 × 5 array in the fabricated 32 × 32 ECRAM array. Adapted with permission [64]. Copyright 2021, IEEE. c Diagram of parallel update (PU) (top) and sequential update (SU) operations in n x n ECRAM array (bottom) [109]. d Determined E ratio in relation to the size of the array. Reducing ISD at a specific IGS will minimize the ratio [109]. e Block schematic of the neuromorphic system with a three-terminal ECRAM array [110]