Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs)

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal–oxide–semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high-k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high-k etching process.


Background
The steady scaling-down of semiconductor device with rapid progress of fabrication technology facilitated high-integration, high-performance [1]. However, scaling-down resulted in short channel effects and power consumption increased exponentially [2,3]. Recently, low power consumption becomes one of the most important requirements as scaling-down in semiconductor industry with the rapid growth of mobile market.
The most efficient way to reduce power consumption is to scaling supply voltage (V DD ) down which plays an important role in determining both standby and dynamic power consumptions. However, V DD scaling of MOSFETs has been slower than device scaling because the downscaling of threshold voltage (V T ) leads to a dramatic increase of off-current (I off ) as described in Fig. 1 [4]. This is closely related to fundamental limit that subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec [5]. In the case of MOSFETs, carriers are injected from the source to the channel by thermionic emission mechanism. As the energy distribution of conduction electrons in the source follows the Fermi-Dirac distribution, electrons injected by increasing gate voltage (V G ) also follow the Fermi-Dirac distribution which limits minimal SS around 60 mV/dec at room temperature.
In this thesis, hetero-gate-dielectric tunneling fieldeffect transistors (HG TFETs) are investigated. HG TFETs show higher I on , lower ambipolar current (I amb ) and smaller SS than conventional TFETs by replacing sourceside gate insulator with high-k materials [18]. First, the theoretical background of TFETs and device concepts of HG TFETs will be covered. In addition, HG TFET design was optimized and improved through the simulation. As a result, HG TFETs showed higher performance than that of conventional TFETs. To improve the performance of HG TFETs, improved fabrication methods were proposed. Etching the gate insulator at the source side by using HF vapor improved enlargement of etched gate insulator thickness. In addition, structure of sidewall spacers was changed to remove the high-k layer on the source region by high-k etching process. This solved the problem that tunneling barrier width was increased by fringe field. After the overall process flow for the fabricating HG TFETs using standard CMOS process was introduced, electrical characteristic results of fabricated device demonstrated the simulation results. Proposed HG TFETs showed higher performance than our previous results. As a result, it is concluded that HG TFETs are promising to be used for highly energy efficient ICs.

Basic operations of TFETs
Compared to MOSFETs, basic structure of TFETs is a gated p-i-n diode as shown in Fig. 2. Band-to-band tunneling mechanism is used as a carrier injection of TFETs instead of thermionic emission. Different operation mechanism between MOSFETs and TFETs comes from the asymmetric doping profile of source and drain of TFETs. In n-channel TFETs, the p + source is grounded and the n + drain is positively biased. In the off-state, TFETs resemble a reverse biased p-i-n diode and tunneling barrier width (W tun ) between valence band of the source and conduction band of the channel is thick which make extremely low I off flow. In the case of MOSFETs, electron injection from the source to the channel is hard because of high energy barrier between the source and the channel. In the on-state, when a positive gate bias induces strong band bending of channel and W tun is narrowed, the valence band electrons from the source region tunnel through the barrier into the conduction band in the channel region. Thus, the TFET shows very sharp on-off transition and SS value of TFETs is not subjected to 60 mV/dec thermal limit like MOSFETs. These characteristics lead a TFET as one of the most promising candidates for low-power device. Despite those advantages, TFETs have several disadvantages to figure out. Because of high tunneling resistance, I on of TFETs is much lower than that of MOSFETs and ambipolar behavior of TFETs increases leakage current [8]. To improve performance of TFETs, various techniques have been proposed. Since I on of TFETs is determined by W tun and electric field at the tunneling junction, introducing high-k materials as a gate insulator, narrow bandgap materials and novel device structures were shown. However, using high-k materials as a gate insulator increases I amb by ambipolar behavior as well as I on [14].

Characteristics of HG TFETs
HG TFETs are proposed for higher I on , lower I amb , and smaller SS. In this study, HG TFETs will be compared with two kinds of conventional TFETs, high-k-only and SiO 2only TFETs as shown in Fig. 3. High-k-only TFETs use only high-k dielectric as gate insulator and SiO 2 -only TFETs use only silicon oxide (SiO 2 ) as a gate insulator. The HG TFET is composed of different gate dielectric materials at the source and drain sides. A high-k material is only partially located at the source side and this leads to the particular energy band structure as shown in Fig. 4. HG TFETs show a local minimum of the conduction band edge (E c ) due to relative permittivity discrepancy between high-k dielectric and SiO 2 layer. HG TFETs show more abrupt change from off to on-state because W tun of HG TFETs abruptly narrows when a local minimum of E c is aligned with the valence band edge (E v ) of the source region.
To compare the performance of HG TFETs with highk-only and SiO 2 -only TFETs, two-dimensional device simulation has been performed by using Silvaco ATLAS [24]. A nonlocal band-to-band tunneling model has been used. Band gap narrowing, Fermi statistics, Shockley-Read-Hall (SRH) recombination and Lombardi mobility models have been used in this simulation. Gate leakage current and quantum effect have been ignored. An abrupt source/drain junction profile has been assumed as shown in the previous works [18,25]. Device parameters used in this simulation are summarized in Table 1. Figure 5a shows the transfer characteristics of HG, high-k-only and SiO 2 -only TEFTs that use n-type doped polysilicon gates. Optimized HG TFETs whose length of high-k material under the gate (L high-k ) is 5 nm are used in this case. HG TFETs follows SiO 2 -only TFETs at low V G because ambipolar behavior is determined by the drain-to-channel region overlapped by SiO 2 layer. On the other hand, onstate of HG TFETs follow high-k-only TFETs because of high-k insulator locate at the source-to-channel region. For fair comparison, the gate workfunction is adjusted that I off is 0.1 fA at 0 V V G as shown in Fig. 5b. Because HG TFETs show higher I on than high-k-only TFETs and have I amb as low as SiO 2 -only TFETs, HG TFETs show lower SS than high-k-only and SiO 2 -only TFETs.

Optimization of the device design
To optimize the device design of HG TFETs, the design issues of HG TFETs such as L high-k and silicon-on-insulator (SOI) layer thickness (T SOI ) have been investigated. I on is defined as drain current (I D ) when both V G and drain voltage (V D ) are 0.7 V, I amb is defined as I D when V G is −0.7 V and V D is 0.7 V. SS is defined as an average slope when I D is from 0.1 fA/μm to 0.1 nA/μm at V D is 0.7 V. Figure 6a shows extracted I on and SS as a function of L high-k . When L high-k is optimized around 5 nm, HG TFET show ~40 % smaller SS and three times higher I on than high-k-only TFETs. In addition, HG TFETs show ~70 % smaller SS and three orders of magnitude higher I on than SiO 2 -only TFETs. Figure 6b shows extracted I amb as a function of L high-k . Because I amb is determined by ambipolar behavior at the drain side, I amb abruptly decrease as L high-k decreases. As a result, HG TFETs show six orders lower I amb compared to highk-only TFETs.
In addition, the effect of T SOI has been discussed in terms of I on and SS. Figure 7 shows extracted I on and SS as a function of T SOI for several different operating voltage (V DD ). I on is defined as I D when both V G and V D are equal to V DD . SS is defined as same as before. I on of HG TFETs show little change as T SOI decreasing when V DD is 0.7 V. However, I on of HG TFETs tends to become lower as T SOI decreases at low V DD as shown in Fig. 7b, c. In addition, decreasing T SOI makes the SS of HG TFETs larger regardless of V DD . It is because the performance of HG TFETs is mainly determined by the difference in the gate-to-channel coupling strength between channel regions overlapped by the high-k insulator and SiO 2 layer and it decreases as T SOI decreases. As a result, it is difficult to form a local minimum on the conduction band edge and performance of HG TFETs worsens as T SOI decreases. To sum up, large T SOI can be helpful to get higher I on of HG TFETs at low V DD and SS of HG TFETs increases as T SOI decreases regardless of V DD [26]. As a result, 30-nm T SOI is selected for fabrication this time.

Improvement in device design
Our previous work showed worse HG TFET performance than expected [27]. It was concluded that this result came from some factors: gradual doping profile, enlarged highk dielectric thickness at the source side and sidewall spacer structures. All of these factors are related to the fabrication process and these have been investigated to improve the performance of HG TFETs.
First, abrupt doping profile at the tunneling junction is very important for TFETs because it determines W tun and electric field which control the tunneling current. Doping  profile which is especially overlapped by high-k material has an influence on HG TFETs because performance of HG TFETs is mostly determined by formation of a local minimum of the E c at the tunneling junction [18]. As a result, abrupt doping profiles at the tunneling junction are suitable for higher I on and lower SS. However, gradual doping profiles are applied to our HG TFETs because we used conventional RTA instead of advanced annealing method. Thus, fabrication conditions which control the doping profile should be optimized. In general, doping profiles at the tunneling junction are influenced by the spacer length (L spacer ) and the RTA time (T RTA ). L spacer is the sum of an inner high-k spacer length and an outer low-k spacer length. To adopt the fabrication conditions, two-dimensional semiconductor process simulation and device simulation has been performed by using Silvaco ATHENA and ATLAS [24]. In the case of process simulation, some conditions were changed from the conditions used for device simulation. Abrupt doping profile is changed to gradual doping profile which is determined by T RTA . Second, high-k dielectric partially located at the source side increase the gate-to-channel coupling strength and this leads to the particular energy band structure [18]. HG TFETs show lower SS and higher I on because of a local minimum of the E c at the tunneling region. Though the thickness of high-k dielectric should be equal to T ox , this is enlarged during etch process of SiO 2 gate insulator. Thus, the difference of the gate-to-channel coupling strength between channel regions overlapped by the high-k dielectric and SiO 2 decreased. It degrades the performance of HG TFETs and solution to this will be discussed in chapter 3.
Third, the sidewall spacer structure of our previous HG TFETs is problematic. Figure 8a shows the structure of our previous HG TFETs. Previous HG TFETs have gradual doping profiles and dual-k spacers which consist of 3-nm inner high-k spacers and 19-nm outer low-k spacers. High-k spacers are used to enhance the electric field around the tunneling junction and low-k spacers are used to control tunneling junctions [28,29]. However, 3-nm high-k dielectric layers under the low-k spacers are the main factors which degrade the performance of HG TFETs. Because high-k dielectric layers are placed on the source regions, fringe field from gates increases as V G increases. Accordingly, the energy bands of the source regions decrease as well as those of the channel regions. It makes W tun larger and our previous HG TFET performance worse.
To enhance the performance of HG TFETs, the dependency of sidewall spacer structures on the performance has been examined. The structure of a dual-k spacer is improved as shown in Fig. 8b. A 3-nm high-k dielectric layer under the low-k spacer is removed and only a 3-nm inner high-k spacer is remained. To investigate the impact of the dual-k spacer structure on the performance of HG TFETs, fringe field around the tunneling region is compared as shown in Fig. 9. Inner high-k spacer increases the fringe field around the tunneling junction for both structures. Fringe field coupling through the inner highk spacer decreases W tun [28]. However, fringe fields are denser and higher near the junction in the proposed HG TFETs compared to the previous HG TFETs. In the case of proposed HG TFETs, fringe field is focused on the edge of the high-k spacer which is in contact with TEOS spacer. On the other hand, fringe field of the previous HG TFETs is low and spread because fringe field through the inner high-k spacer and high-k dielectric layer under the low-k spacer are balanced. Thus, gate potential is coupled over a large distance and this result in low current.
The impact of the fringe field coupling on the tunneling region is further illustrated by the band diagrams as shown in Fig. 10. The figure shows the band diagrams near the tunneling junction for V G = V D = 0.7 V. From the figure, W tun of the previous and proposed HG TFETs have been compared each other. As mentioned before, W tun of the previous HG TFETs is larger than that of proposed HG TFETs because fringe field through the highk dielectric layer on the source region reduce the energy band of the source region.
To optimize the design of HG TFETs, the effect of variation in the length of the high-k spacer on I on has been investigated. Figure 11 shows the transfer characteristics of the proposed HG TFETs compared with the previous HG TFETs as the length of the high-k spacer varies from 0 to 5 nm. The length of an outer low-k spacer is fixed at 19 nm for all because of the tunneling junction. Performance degradation is more severe in the case of the previous HG TFETs because high-k dielectric on the source region increases the coupling between the gate and the source region. It is clear from the transfer characteristics in Fig. 11 that the device performance degrades with an increasing the length of the high-k spacer for the proposed HG TFETs. An increase in the length of the high-k spacer reduces the electric field from the gate because of the physical distance, thereby causing the degradation in the device performance. Figure 12 shows the energy band diagrams of the proposed HG TFETs with various high-k spacer lengths at V G = V D = 0.7 V. W tun was extracted from the point which shows the maximum electron tunneling rate. W tun increases as the length of the high-k spacer increases which is consistent with the trend in the transfer characteristics. As a result, HG TFETs without an inner high-k spacer show the most improved performance. However, the length of high-k spacer in this study is 3 nm because of the fabrication issues and this will be covered in chapter 3.   To verify the fabrication condition for the proposed HG TFETs, the effects of L spacer and T RTA have been also discussed in terms of I on and SS. Figure 13a shows extracted SS as a function of L spacer and T RTA . When the device structure is formed by process simulation, SS is extracted from different range of I D because leakage current level and average of SS are higher than those of device simulation. Thus, SS is defined as an average slope when I D increases from 10 to 100 fA/μm. Regardless of T RTA , SS of HG TFETs becomes higher as L spacer decreases because dopants of high concentration diffused from the source region are overlapped by high-k material. In this case, conduction band well becomes shallower because higher doping concentration makes E c under the high-k material increases. On the other hands, SS becomes higher as L spacer increases because of underlap between source and channel region. Similarly, when L spacer is fixed, SS becomes higher as T RTA decreases because of underlap structure. On the contrary, as T RTA increases, conduction band well becomes shallower, which makes less abrupt transition between off-and on-state. When T RTA is 3 s, minimum SS value is shown when L spacer is 24 nm and optimum L spacer increases as T RTA increases. Figure 13b shows extracted I on as a function of L spacer and T RTA . The turn-on voltage (V turn-on ) is defined as V G when I D is 10 fA/μm. I on is defined as I D when V D is 0.7 V and V G is 0.7 V higher than V turn-on . I on shows similar tendency observed in SS as a function of L spacer and T RTA . Optimum L spacer increases as T RTA increases for the same reason. Tunneling current increases as electric field at the tunneling region increases and it is reversely exponential to W tun . Electric field is determined by the slope of the energy level in the band diagrams and W tun is also strongly influenced by doping profiles. Mostly optimized I on is shown when T RTA is 3 s because more abrupt doping profile is formed as T RTA decreases. When T RTA is 3 s, optimum L spacer is 24 nm as same as in the case of SS.
From the results of simulation, overlapped region between Fig. 13a, b is selected as the target for the fabrication condition. Finally, optimized L spacer is 24 nm and T RTA is 3 s. Though there is variability from the fabrication conditions, it would be within the margin of error because SS shows little change.

Improvement in fabrication methods
As discussed in chapter 2, performance degradation was shown for previous HG TFETs and reasons are closely related to fabrication issues. Gradual doping profile is one of them and it is difficult to be improved because it needs advanced annealing equipments. However, there are solutions for enlarged high-k dielectric thickness at the source side and the structure of the sidewall spacer. Two key ideas have been introduced to enhance the performance of HG TFETs in this work. Figure 14 shows the key process flow to form HG and spacer structure of previous and proposed HG TFETs. In previous work, 7:1 BHF solution was used to etch SiO 2 gate insulator. However, this method increased the thickness of the etched SiO 2 gate insulator which would be filled with high-k material. Because BHF etched n + -doped polysilicon as well as SiO 2 gate insulator, corner of the gate was also etched. As a result, thickness of HfO 2 (T HfO 2 ) was larger than thickness of SiO 2 layer (T SiO 2 ) especially at the edge of the polysilicon gate. This decreased difference of gate-to-channel coupling strength between channel regions overlapped by the high-k material and SiO 2 layer which mainly determines the performance of HG TFETs. This problem has been improved by using HF vapor to etch the SiO 2 gate insulator at the source side. HF vapor showed much better selectivity compared to 7:1 BHF solution and it enhanced thickness uniformity between T HfO2 and T SiO2 . While etching the SiO 2 insulator, the sample was held at 40 °C. It is because etch rate is too high to control and uniformity is bad when the temperature is lower than 40 °C and etch rate is too low when the temperature is higher than 40 °C.
Additionally, process for formation of the HG structure has been changed to remove the high-k dielectric layer on the source region. In previous work, outer TEOS spacers were formed right after HfO 2 ALD process and then residual HfO 2 was removed. As a result, HfO 2 layers were remained under TEOS spacers and this decreased energy band of the source region because of increased fringe field from the gate when gate bias is applied [28]. This led to increase of W tun and degraded performance of HG TFETs. This problem has been improved by etching HfO 2 layers before TEOS spacers were formed. In this case, anisotropic HfO 2 etching process should be defined to protect the HfO 2 layer inserted under the gate. Thus, inductively coupled plasma (ICP) dry etcher was used to etch HfO 2 layer on the source region. Adjusting etching time is very important because HfO 2 layer on the source region should be removed and HfO 2 layer under the gate should be protected at the same time. In addition, very careful control of HfO 2 dry etch process was needed because silicon under the HfO 2 layerrewis also etched well by HfO 2 etch process condition (BCl 3 100 sccm, 700 W, 5 Wb, 10 mtorr). As a result, HfO 2 layers on the source region were removed and 3-nm inner HfO 2 spacers were remained finally.

Device fabrication
In order to fabricate HG TFETs without complexity, the fabrication followed the standard CMOS process. Figure 15 shows key process flow for the fabrication of HG TFETs on SOI wafers. Most of the process steps and device structures are similar to those in previous work [27]. However, performance of fabricated HG TFETs have been improved by changing the method of etching SiO 2 layer in Fig. 15d and changing the order of sidewall spacer formation and HfO 2 dry etching. P-type (100) 6-inch SOI wafers (T SOI = 100 nm and T BOX = 375 nm) were prepared to reduce the leakage current and T SOI was reduced to be 30 nm by thermal oxidation and removing oxide layer. Active patterns were formed on SOI substrate by photolithography and dry etching. Mesa isolation was used to separate each active region by BOX layer. The channel region is doped with p-type at 10 15 cm −3 . By dry oxidation and low-pressure chemical vapor deposition (LPCVD) process, the gate stack of 5-nm-thick SiO 2 layer and 100-nm-thick phosphorusdoped polysilicon gate was formed over the active patterned substrate. The most important key process flow of HG TFETs is formation of the HG structure which is divided into two steps. First, SiO 2 gate insulator of source side was selectively etched by using HF vapor. Before etching the SiO 2 gate insulator only in the source side, photolithography step was performed by using mask for protecting the drain region. Second, atomic layer deposition (ALD) of 5-nm-thick HfO 2 was performed to fill the etched gate insulator with high-k material. Then, HfO 2 was etched anisotropically to remove the HfO 2 on the gate, source and drain regions. Next, sidewall spacer was formed with deposition and etching of TEOS layer. TEOS layer was deposited using PECVD and etched by reactive ion etch (RIE). Next, asymmetric source and doping profiles were obtained by implanting different ions respectively. Compared to MOSFETs which are implemented by self-aligned source and drain ion implantation, two clear field masks for implantation to the source and the drain regions are required as shown in Fig. 16. Each mask for covering source and drain regions during implantation is described with different dotted lines. The mask for implantation to source region is the same as the one which is used when source side SiO 2 gate insulator was selectively etched by HF vapor. Mask for implantation to the source region was designed to cover the contact area of the gate region, because gate was doped with n-type and source region was implanted with p-type. Low energy ion implantation was performed for both source and drain regions to form a steep junction profile. After photolithography for implanting source region was performed, BF 2 ions were implanted with a dose of 1 × 10 15 cm −2 at 5 keV. Following photoresist stripping, photolithography for implanting drain region was performed and As was implanted with the same condition as implantation for source region. In order to activate the dopants with minimal dopant diffusion, rapid thermal annealing (RTA) was done at 1000 °C for 3 s. As an interlayer dielectric (ILD) layer, 200-nm-thick TEOS layer was deposited by PECVD which is followed by photolithography for contact hole. Using the photoresist as a mask, ILD was etched down to the gate, source and drain regions by RIE. For a pre metal cleaning, 50:1 Fig. 15 Key process for the fabrication of proposed HG TFETs buffered hydrogen fluoride (BHF) solution was used for 30 s. Then, a four-level metallization (Ti-TiN-Al-TiN) was carried out in a sputtering system. Ti was used for metal adhesion, TiN was used for barrier metal, and TiN was used as an antireflection coating for photolithography of Al metal line. Metal pads were defined by photolithography and etch process. In the final step, forming gas annealing was performed at 450 °C for 30 min in H 2 /N 2 ambient. Figure 16 shows the top view scanning electron microscope (SEM) image of the fabricated HG TFET. Gate length and width are 1 and 2.7 μm, respectively. Figure 17 shows the cross-sectional transmission electron microscope (TEM) image of the fabricated HG TFET. L high-k of the fabricated HG TFET is ~8 nm which is similar to the optimized value [18]. Additionally, the increase of T HfO 2 at the source was improved and HfO 2 layer on the source was removed in the proposed HG TFETs as shown in Fig. 17. T HfO 2 is almost equal to T SiO 2 . The spacers consist of 3-nm-wide inner HfO 2 spacers and 20-nm-wide outer TEOS spacers. In order to evaluate the merits of HG TFETs, SiO 2 -only TFETs were also fabricated as control devices. Most of the process flow was the same as that of HG TFETs except for the formation of the HG structure. The SiO 2 -only TFET has only 20-nm TEOS spacers. Figure 18 illustrates the transfer curves of the proposed HG TFETs compared with those of previous HG TFETs and SiO 2 -only TFETs for V D = 0.1 and 1.0 V. Proposed HG TFETs show higher I on and lower SS than previous HG TFETs as a result of improved device design even though t ox is 5 nm which is larger than 3-nm t ox of previous HG TFETs. In addition, proposed and previous HG TFETs show much higher I on and lower SS than SiO 2only TFETs because HG TFETs have a local minimum of E C resulted from locally inserted HfO 2 at the source side gate dielectric. This reduces W tun and increases the electric field at the tunneling junction. Though both HG and SiO 2 -only TFETs show low I off , I amb of both kinds of devices increases as V D increases. Especially, I amb of HG TFETs is larger than that of SiO 2 -only TFETs because  inner high-k spacers reduce W tun between drain and channel region as well as W tun between source and channel region. Thus, the underlap structure between gate and drain or reducing drain doping concentration are needed to reduce I amb [16,17]. Figure 19 shows the output characteristics of the proposed and previous HG TFETs. The output characteristics of proposed HG TFETs show better performance and lower parasitic resistance than previous HG TFETs. I D of both kinds of HG TFETs increases with V D slowly until it reaches its saturation value at high V D because of high tunneling resistance. Especially, the tunneling resistance of previous HG TFETs is higher than proposed HG TFETs because W tun is larger than proposed HG TFETs.

Electrical characteristics
Output characteristics of TFETs are different from those of MOSFETs because their mechanisms are different. While MOSFETs are saturated when the inversion layer of drain side is disappeared, most of inversion layer of TFETs is formed from the drain and surface channel potential (Ψ s ) is pinned by V D [30]. Thus, inversion layer formation makes I D less sensitive to V G and low V D results in low Ψ s which induces band-to-band tunneling currents. However, saturated currents become sensitive to V G because I D is determined by band-to-band tunneling without V D influence when I D is saturated. Figure 20 shows SS of proposed and previous HG TFETs in terms of I D . SS of SiO 2 -only TFETs is not considered because SS is much higher than those of both HG TFETs. Proposed HG TFETs show lower SS within wider current range than previous HG TFETs. Table 2 summarizes electrical characteristics of proposed HG TFET compared with those of previous HG TFET and SiO 2 -only TFET. Dimensions of proposed HG TFET are same as previous HG TFET but T ox is different at this time. I off is defined as I D is equal to 1pA/μm and V off is defined as the V G when I D is I off . I on is defined as I D when V G is V off + V DD . SS min is minimum point swing and SS avg is an average slope when I D is from 1pA/μm to 1nA/μm. Proposed HG TFET shows higher I on and lower I min than previous HG TFET even though T ox is increased. SS min and SS avg of proposed HG TFET are also lower than those of previous HG TFET. In addition, proposed HG TFET has an I on /I off of 5.6 × 10 4 at V DD = 1 V which is comparable with other reported Si TFETs [8,11,12,22].
Although HG TFETs are proposed for low-power application, SS of HG TFETs is larger than 60 mV/dec and current drivability is much smaller than requirements of the Low Standby Power devices [31]. First of all, abrupt doping profile is necessary for higher I on and lower SS. Because conventional RTA is used in this work, W tun is increased and it is difficult to control the tunneling junction. Advanced annealing methods such as spike or