Accurate extraction of WSe2 FETs parameters by using pulsed I-V method at various temperatures

This work investigates the intrinsic characteristics of multilayer WSe2 field effect transistors (FETs) by analysing Pulsed I-V (PIV) and DC characteristics measured at various temperatures. In DC measurement, unwanted charge trapping due to the gate bias stress results in I-V curves different from the intrinsic characteristic. However, PIV reduces the effect of gate bias stress so that intrinsic characteristic of WSe2 FETs is obtained. The parameters such as hysteresis, field effect mobility (μeff), subthreshold slope (SS), and threshold voltage (V th) measured by PIV are significantly different from those obtained by DC measurement. In PIV results, the hysteresis is considerably reduced compared with DC measurement, because the charge trapping effect is significantly reduced. With increasing temperature, the field effect mobility (μeff) and subthreshold swing (SS) are deteriorated, and threshold voltage (V th) decreases.


Background
Two-dimensional(2D) layered materials such as graphene and boron nitride offer new opportunities in the field of electronics with its excellent physical, chemical properties [1][2][3][4][5][6]. Though graphene has been studied most widely, its lack of bandgap limits its application. Transition metal dichalcogenides (TMDCs) provide a solution to this problem with their sizable bandgap energy and ultra-thin form of layers. Among them, WSe 2 FETs can be very appealing for the nanoscale electronic applications and blackplanes for flat panel display (FPD) due to their high mobility (~100 cm 2 /V·s), excellent on/off ratio(~10 7 ), and low subthreshold swing (SS, ~70 mV/ decade) [7][8][9].
When we simulate the circuits which consist of WSe 2 FETs, it is necessary to know the parameters of the FETs. Most of the parameters reported up to now were extracted from the I-V characteristics obtained by the DC method. However, these values were not correct, because a large hysteresis is observed due to the gate bias stress during the DC measurement [10][11][12]. On the other hand, in the Pulsed I-V (PIV) measurement, the effect of gate bias stress is reduced greatly so that intrinsic characteristic of WSe 2 FETs can be obtained [13,14]. Thus PIV method is considered as a reasonable method for estimating the performance and reliability of semiconductor devices. The purpose of PIV method is to avoid the negative effects such as self-heating and transient trapped charges. Therefore, the PIV method can provide the accurate device parameters needed for improved computer-aided-engineering (CAE) software models. However, there have been no reports on the parameter extraction from the fabricated WSe 2 FETs at various temperatures. In this work, we show the I-V curves measured by PIV and DC measurement methods, and compare the parameters extracted from the results obtained by both methods at various temperatures (−30 to 40 °C). Figure 1 shows the perspective view of the structure of a multilayer WSe 2 FET with the bottom gate structure. An n-type silicon wafer which was heavily doped (ρ ~ 0.005 Ω·cm) by phosphorus is used as a starting substrate and also plays a role as back-gate electrodes. After thermal Open Access *Correspondence: jhl@snu.ac.kr Department of Electrical and Computer Engineering, Seoul National University, Seoul 151-747, South Korea oxidation in dry oxygen at 950 °C, 35 nm thick thermal oxide which serves as gate insulator was grown on the heavily doped Si wafer. Then, WSe 2 flakes were mechanically exfoliated from bulk WSe 2 crystals and transferred on SiO 2 /Si substrate by using a polydimethylsiloxane (PDMS) stamp. The multi-layer WSe 2 flakes on the substrate were annealed at 350 °C for 2 h in the ambient of a mixed gas of argon and hydrogen. Photolithographic patterning and electron beam evaporation of Pd (~70 nm), followed by lift-off in acetone, create source and drain electrodes on the WSe 2 flakes with a good Ohmic contact. However, one of the key limitations for TMDC devices, like other types of low-dimensional material, comes from the intrinsic nature of instability associated with easy adsorption of gaseous molecules such as oxygen and moisture due to the large surface areas of lowdimensional materials. Absorbed gaseous molecules and moisture can act as a charge trap site [15]. To prevent the molecules being absorbed, we adopted flourinated polymer (CYTOP; CTL-809 M, Asahi Glass Co., Ltd) passivation so that the drift of the drain current in MoS 2 FETs was reduced greatly [16]. Therefore, the backside of the WSe 2 flake was encapsulated by the CYTOP with typical spin coating process. Then, after thermal evaporation of SiOx(~50 nm) on the CYTOP, for a surface promoter layer during PR coating, pad opening was completed by dry etching(~SF 6 /CF 4 ) via PR patterns. Figure 2 shows the transfer curves (I D -V GS ) measured at 20 °C from the FET with a W/L of 30/10 μm at a drainto-source voltage (V DS ) of −0.1 V. We carried out the measurement using WGFMU (Waveform Generator and Fast Measurement Unit) module installed in an Agilent B1500 semiconductor parameter analyser. In DC and PIV measurement, the V GS is scanned from 3 to −3 V (forward) and then from −3 to 3 V (reverse). The transfer curves obtained by DC measurement show a large hysteresis. Because of the V GS stress during the DC measurement, the charges can be trapped or de-trapped at the WSe 2 / SiO 2 interface and/or the backside of WSe 2 flakes, therefore the threshold voltage (V th ) can be shifted positively or negatively. In Fig. 2, we can clearly observe the hysteresis in DC I D -V GS curves represented by square symbols, but not in the PIV curves. The drain currents measured by the DC method are smaller than those measured by the PIV method when the V GS is larger than V th in magnitude. If we extract the carrier mobility from the DC I D -V GS curves, the mobility seems to be degraded. Since some of the trapped charges stay trapped until the gate polarity is switched in the DC measurement, the large hysteresis is observed in DC measurement [17]. Note the off-current obtained by the PIV method is much higher than that obtained by the DC method in Fig. 2 because the low limit of the WGFMU module in measurement current is ~10 −8 A. In PIV measurement, we investigated the optimized condition to reduce gate bias stress as small as possible. Figure 3a, b depict bias scheme for the DC and Pulsed I-V measurements, respectively. The t sw in the inset of Fig. 3a represents the step width at each bias step. The drain bias (V DS ) is fixed at −0.1 V from the start of the measurement. The t on , t off , and V base in the inset of Fig. 3b stand for turn-on pulse width (10 −4 s), turn-off pulse width (1 s), and the bias during turn-off (0 V), respectively [17]. During the period, both rise and fall times are 10 −7 s. The V GS pulse during t off is set to 0 V to minimize the V GS stress effect. Shorter t on and longer t off are necessary to suppress the effect of the trapping and detrapping of the charges. Note the drain bias is synchronized with the gate bias and the bias is −0.1 V during t on .  Fig. 2, the hysteresis is much suppressed by measuring the device with the PIV method. Mobility (μ eff ), subthreshold swing (SS), V th are extracted from the transfer curves at various temperatures.

Result and discussion
In Fig. 5, shown is temperature dependency of electrical parameters extracted from transfer curves of multilayer WSe 2 FETs. In Fig. 5a, the hysteresis is clearly observed in the I D -V GS curves obtained by DC method, but ignorable hysteresis in the curves measured by PIV method. The hysteresis was defined as the V GS difference at a fixed drain current of 10 −8 A between the forward and reverse scans. Electrons or holes during the measurement of the DC method can be trapped or detrapped into the traps at the interface due to V GS stress, which leads to a positive or negative shift in the V th . As the temperature increases, the hysteresis in the curves measured by DC method increases because elevated temperature activates the trapping and detrapping process of carriers.
It seems that the time constants for the carrier trapping and detrapping in given temperature range are longer than the t on (10 −4 s) used in this work so that the increase of hysteresis during PIV method can be ignorable. The variation of the hysteresis with the t on was studied in [17]. Figure 5b shows the temperature dependency of mobility. The field effect mobility was extracted from the maximum point of transconductance (g m ) using the following equation where C and g m are gate capacitance per unit area and the transconductance, respectively. The μ eff was deteriorated as the temperature increases from −30 to 40 °C. Phonon scattering is enhanced with rising temperature, which leads to the degradation in the carrier mobility. According to the relation of μ eff ∝ T −γ , the γs for the forward and reverse scans are 1.149 and 0.682, respectively. However, the decrease rate obtained by the PIV is 0.646. The mobility measured by PIV method is greater than the mobility measured by DC method, because in the DC measurement hole was trapped and it decreases the current, which decreases apparently the effective mobility. However, in Pulsed I-V measurement, the trapped hole was detrapped during t off and the mobility was not degraded appreciably. Besides, mobility measured in DC forward scan is lower than the mobility measured in DC reverse scan. The hole density in the channel is reduced due to the charge (hole) trapping during DC forward scan, so the slope of I-V curves is reduced, which results in reduced mobility. During DC reverse scan, the discharging is mainly occurred by hole emission to the valance band. The holes need some energy to be emitted to the valence band. Therefore, the traps do not discharge significantly until the gate bias is below threshold voltage (V th ), so the carrier density in the channel is reduced.
In addition, as the temperature rises, the difference between the mobility measured by DC forward and reverse scans increases as shown in Fig. 5b. The reason for the difference is explained as follows. Compared to the case of the forward scan, the holes in the reverse scan are increasingly emitted to the valence band with increasing temperature since increasing temperature increases the energy of the holes trapped. Figure 5c shows subthreshold swing (SS) measured at various temperatures. The SS was defined as V GS1 (V GS at I d = 10 −9 A)-V GS2 (V GS at I d = 10 −8 A). As temperature increases, the SS increases as given by SS measured by DC measurement is greater than SS measured by PIV, because charge trapping decreases the current in DC measurement which makes SS larger. Furthermore, SS measured by DC forward scan is larger than the SS measured by DC reverse scan, because as explained above the slope of DC forward scan is smaller than that of DC reverse scan. The difference between SS measured by DC forward scan and SS measured by DC reverse scan increases as temperature rises. This