Scalability of Schottky barrier metal-oxide-semiconductor transistors
© The Author(s). 2016
Received: 19 January 2016
Accepted: 26 April 2016
Published: 16 May 2016
In this paper, the general characteristics and the scalability of Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are introduced and reviewed. The most important factors, i.e., interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are estimated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are estimated as 1.5 × 1013 traps/cm2, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by N2 annealing. Based on the diode characteristics, various sizes of erbium-silicided/platinum-silicided n/p-type SB-MOSFETs are manufactured and analyzed. The manufactured SB-MOSFETs show enhanced drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are comparable with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.
Recently, semiconductor–metal junction-based electronic devices are being studied for the applications in nanometer regime as the alternative of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) [1–6]. In Schottky barrier MOSFETs (SB-MOSFETs), the source and drain are composed of silicide instead of impurity doped silicon. Thus the parasitic source and drain resistance can be efficiently eliminated and the process temperature can be reduced dramatically lower than 600 °C, giving the opportunity to use metal as gate electrode and high-K dielectric materials as gate insulator [1–4]. However, in SB-MOSFETs, silicon in channel region reacts with the deposited metals. This reaction can cause the generation of trap states, causing microscopic inhomogeneity of Schottky barrier height . Thus, for the improvement of the device performance, the interface of Schottky diode should be carefully analyzed. Until now, current–voltage (I–V) measurement method has been widely used to explore the trap states in Schottky diode by evaluating diode ideality factor [7, 8]. However, there has been no established method on the quantitative evaluation of trap density in the Schottky diode, although it is well established in the metal-insulator-semiconductor system .
In SB-MOSFETs, most of the works are done in p-type transistors, using platinum-silicide because of its low Schottky barrier height (0.24 eV) for hole . Although there are few works on n-type SB-MOSFETs, erbium-silicide is being considered as the promising candidate for the n-type SB-MOSFETs [5, 6]. However, erbium-silicide could generate heavy trap sites at silicon/erbium silicide interface. Thus, the study on the erbium-silicided Schottky diode characteristics, incorporating trap states with Schottky barrier height and their effects on the electrical characteristics of SB-MOSFETs are very important.
In this paper, the detailed characteristics of erbium-silicided Schottky diode, fabricated on the p-type silicon are introduced and the interface of Schottky diode is analyzed using the current–voltage and capacitance–voltage (C–V) measurement methods. Moreover, by incorporating equivalent circuit model with the C–V measurement method, trap density, lifetime and Schottky barrier height are extracted in erbium-silicided Schottky diode. Also, short channel characteristics of SB-MOSFETs are analyzed using drain induced barrier lowering (DIBL) and subthreshold swing (SS) characteristics. Also, the simple DIBL model of SB-MOSFETs is proposed and compared with the scaling theory of double gate (DG) MOSFETs.
2.1 Fabrication of erbium-silicided Schottky diode
In conventional MOSFETs, Titanium, Cobalt and Nickel are widely being used for the silicidation process to minimize the parasitic resistance of impurity doped source and drain. But in this work, erbium is chosen as source and drain metal of n-type SB-MOSFETs, because of its low Schottky barrier height (0.28 eV) for electrons [5, 6]. The boron doped (100) p-type bulk silicon wafer is used for the erbium-silicided Schottky diode. The resistivity is 13.5–22.5 Ω cm and the corresponding doping concentration is about 1.0 × 1015 cm−3. After wafer cleaning, 100 nm thick SiO2 layer is grown on the wafers using thermal oxidation method at 1000 °C and the 250 × 250 μm region is opened using lithography and 30:1 BOE (buffered oxide etchant) etching. After erbium sputtering, erbium-silicide is formed by using rapid thermal annealing (RTA) technique. Annealing temperature and time and pressure are 500 °C, 5 min and 1.0 × 10−6 torr, respectively. The non reacted erbium is removed by using the mixture of H2SO4 and H2O2 (Sulfuric Peroxide mixture: SPM) SPM for 10 min. The volume ratio of H2SO4 and H2O2 is 1:1. The thickness of ErSi1.7 is about 55 nm which is confirmed by transmission electron microscopy. Platinum-silicide is formed on the boron heavily doped backside of p-type silicon wafers for ohmic contact for the accuracy of the measurements.
2.2 Fabrication of SB-MOSFETs
3 Results and discussion
3.1 Analysis of erbium-silicided Schottky diode
where, n = 1, 2 for the case of Frenkel-Poole and Schottky emission, respectively. Here, q is the electron charge quantity, k Boltzmann’s constant, ε permittivity, and E the maximum electric field in Schottky diode. The theoretically calculated slopes at 27 °C for Frenkel-Poole and Schottky emission is 0.0087 and 0.0043 (V/cm)−1/2, respectively.
In (2), the plot of G p /ω versus ωτ goes through maximum when ωτ = 1, and gives τ directly. The value of G p /ω at the maximum is C t /2. Thus, equivalent parallel conductance, divided by angular frequency gives C t and τ directly from the measured conductance. The trap density is obtained by using the relation D t = C t /qA, where A is the diode area. By using the extracted value C t in G p /ω relation, C D can be extracted directly by using C p . Also, C t andτ can be evaluated by using C p relation. But in this case, inaccuracy of extracted values can exist because of the sensitive dependence of C p to measured frequency, ω. For the consideration of external resistance including substrate and contact resistance, serial connection of additional resistor can be added.
Figure 4 shows the plot of G p /ω versus frequency with the 0.2 V reverse bias condition. The conductance and capacitance are measured using HP4285A impedance analyzer. In figure, the circle and solid line represent measured and fitted data, respectively. From the curve fitting, the extracted C t , D t and τ value are 2.4 × 10−6 Farads/cm2, 1.5 × 1013 traps/cm2 and 3.75 ms, respectively. The extracted C D value is 10.6 × 10−9 Farads/cm2. The extracted interface-trap density is higher compared with the typical values in SiO2 interface . This interface-trap can be cured using hydrogen annealing.
3.2 Scalability of SB-MOSFETs
In Fig. 9b, dotted line represents theoretical SS characteristics of DG-MOSFETs, with 1 nm gate oxide and 10 nm body thickness. As shown, the SS characteristics of SB-MOSFETs are almost compatible with ultimately scaled DG-MOSFETs. However there exist deviations of DIBL values of SB-MOSFETs from the theoretical prediction. The reason for these deviations are due to the interface trap states between silicon and silicide interface. As analyzed in Fig. 3, most of the trap states contribute to Frenkel-Poole emission which causes the degradation of DIBL and also SS characteristics in SB-MOSFETs. Thus, the control of the interface trap states in SB-MOSFETs are the important key factor for the improvement of DIBL and SS characteristics. One efficient method for the reduction of interface traps is N2 annealing and the detailed method and the results are reported in .
Erbium-silicided Schottky diode is fabricated on the p-type silicon and the electrical characteristics is analyzed using the I–V and C–V measurement methods. From I–V analysis, the major leakage current conduction mechanism of reversely biased Schottky diode is due to the Frenkel-Poole emission originating from the existence of deep trap level in the depletion region of erbium-silicided Schottky diode. The trap density and lifetime are evaluated using equivalent circuit modeling method and the extracted trap density and lifetime are 1.5 × 1013 traps/cm2 and 3.75 ms, respectively. The corrected Schottky barrier height (0.76 eV) is extracted by eliminating the parallel connected capacitance associated with trap using equivalent circuit modeling method. Also, SB-MOSFETs are manufactured and the electrical characteristics are analyzed. In SB-MOSFETs, DIBL is strongly suppressed due to the existence of Schottky barrier between source and channel. DIBL and SS characteristics of SB-MOSFETs are compatible with the ultimately scaled DG-MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime as the alternative to the MOSFETs.
This work was supported by the National Research Foundation of Korea(NRF) Grant funded by the Korean government(MSIP) (NRF-2015R1A4A1041631).
The author declares that he has no competing interests.
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