Open Access

Scalability of Schottky barrier metal-oxide-semiconductor transistors

Nano Convergence20163:11

DOI: 10.1186/s40580-016-0071-0

Received: 19 January 2016

Accepted: 26 April 2016

Published: 16 May 2016


In this paper, the general characteristics and the scalability of Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are introduced and reviewed. The most important factors, i.e., interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are estimated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are estimated as 1.5 × 1013 traps/cm2, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by N2 annealing. Based on the diode characteristics, various sizes of erbium-silicided/platinum-silicided n/p-type SB-MOSFETs are manufactured and analyzed. The manufactured SB-MOSFETs show enhanced drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are comparable with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.


SB-MOSFETs Schottky diode Interface trap Scaling

1 Introduction

Recently, semiconductor–metal junction-based electronic devices are being studied for the applications in nanometer regime as the alternative of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) [16]. In Schottky barrier MOSFETs (SB-MOSFETs), the source and drain are composed of silicide instead of impurity doped silicon. Thus the parasitic source and drain resistance can be efficiently eliminated and the process temperature can be reduced dramatically lower than 600 °C, giving the opportunity to use metal as gate electrode and high-K dielectric materials as gate insulator [14]. However, in SB-MOSFETs, silicon in channel region reacts with the deposited metals. This reaction can cause the generation of trap states, causing microscopic inhomogeneity of Schottky barrier height [7]. Thus, for the improvement of the device performance, the interface of Schottky diode should be carefully analyzed. Until now, current–voltage (IV) measurement method has been widely used to explore the trap states in Schottky diode by evaluating diode ideality factor [7, 8]. However, there has been no established method on the quantitative evaluation of trap density in the Schottky diode, although it is well established in the metal-insulator-semiconductor system [9].

In SB-MOSFETs, most of the works are done in p-type transistors, using platinum-silicide because of its low Schottky barrier height (0.24 eV) for hole [6]. Although there are few works on n-type SB-MOSFETs, erbium-silicide is being considered as the promising candidate for the n-type SB-MOSFETs [5, 6]. However, erbium-silicide could generate heavy trap sites at silicon/erbium silicide interface. Thus, the study on the erbium-silicided Schottky diode characteristics, incorporating trap states with Schottky barrier height and their effects on the electrical characteristics of SB-MOSFETs are very important.

In this paper, the detailed characteristics of erbium-silicided Schottky diode, fabricated on the p-type silicon are introduced and the interface of Schottky diode is analyzed using the current–voltage and capacitance–voltage (CV) measurement methods. Moreover, by incorporating equivalent circuit model with the CV measurement method, trap density, lifetime and Schottky barrier height are extracted in erbium-silicided Schottky diode. Also, short channel characteristics of SB-MOSFETs are analyzed using drain induced barrier lowering (DIBL) and subthreshold swing (SS) characteristics. Also, the simple DIBL model of SB-MOSFETs is proposed and compared with the scaling theory of double gate (DG) MOSFETs.

2 Experimental

2.1 Fabrication of erbium-silicided Schottky diode

In conventional MOSFETs, Titanium, Cobalt and Nickel are widely being used for the silicidation process to minimize the parasitic resistance of impurity doped source and drain. But in this work, erbium is chosen as source and drain metal of n-type SB-MOSFETs, because of its low Schottky barrier height (0.28 eV) for electrons [5, 6]. The boron doped (100) p-type bulk silicon wafer is used for the erbium-silicided Schottky diode. The resistivity is 13.5–22.5 Ω cm and the corresponding doping concentration is about 1.0 × 1015 cm−3. After wafer cleaning, 100 nm thick SiO2 layer is grown on the wafers using thermal oxidation method at 1000 °C and the 250 × 250 μm region is opened using lithography and 30:1 BOE (buffered oxide etchant) etching. After erbium sputtering, erbium-silicide is formed by using rapid thermal annealing (RTA) technique. Annealing temperature and time and pressure are 500 °C, 5 min and 1.0 × 10−6 torr, respectively. The non reacted erbium is removed by using the mixture of H2SO4 and H2O2 (Sulfuric Peroxide mixture: SPM) SPM for 10 min. The volume ratio of H2SO4 and H2O2 is 1:1. The thickness of ErSi1.7 is about 55 nm which is confirmed by transmission electron microscopy. Platinum-silicide is formed on the boron heavily doped backside of p-type silicon wafers for ohmic contact for the accuracy of the measurements.

2.2 Fabrication of SB-MOSFETs

As starting material, (100) p-type silicon-on-insulator (SOI) wafer is used. SOI wafer is boron doped with a resistivity of 13.5–22.5 Ω cm and the corresponding doping concentration is about 1.0 × 1015 cm−3. The thickness of the SOI and buried oxide (BOX) layer is 100 and 200 nm, respectively. The gate oxide is 5 nm thick SiO2, grown by thermal oxidation and the gate electrode is highly phosphorus doped n-type polycrystalline silicon. Electron-beam lithography is employed to define gate pattern. After gate etching, 30 nm thick gate sidewall spacer is formed by using thermal oxidation method. After blanket dry etching of gate sidewall spacer, 100 nm thick erbium and platinum are sputtered for n-type and p-type SB-MOSFETs, respectively. Erbium-silicide and platinum-silicide are formed by using rapid thermal annealing (RTA) technique. Annealing temperature and time is 500 °C and 5 min, respectively. The non-reacted erbium and platinum are removed by using SPM and aqua regia for 10 min, respectively. The formation of ErSi1.7 and PtSi phase are confirmed by x-ray diffraction (XRD) and Auger electron spectroscopy (AES) analysis. The sheet resistance are less than 30 and 10 Ω/sq for erbium-silicide and platinum-silicide, even if the line width is less than 100 nm. Thus, erbium and platinum are applicable in nanometer regime SB-MOSFETs manufacturing. The detailed process flow is summarized in Fig. 1.
Fig. 1

Schematic diagram of the fabrication process for Schottky barrier MOSFETs

3 Results and discussion

3.1 Analysis of erbium-silicided Schottky diode

For the erbium-silicide/p-type silicon contact, Schottky barrier heights for hole are extracted as 0.69 and 0.83 eV from IV (Fig. 2a) and CV measurement (Fig. 2b), respectively [10]. The barrier heights determined by two methods give big difference, which causes the difficulty in the determination of Schottky barrier height. On the other hand, from the IV measurement, the extracted ideality factor is 1.23 which implies the possible existence of traps within the depletion region of erbium-silicided Schottky diode. The existence of traps causes the microscopic inhomogeneity of Schottky barrier, which will in turn degrade the ideality factor, thus change the Schottky barrier height [7, 8]. Forwardly biased current transport at inhomogeneous Schottky barrier is dominated by low Schottky barrier patches, leading to the deduction of barrier height. Since, under usual circumstances, the CV method yields an average Schottky barrier height for the whole diode [7]. To analyze the leakage current (I R ) conduction mechanisms in reversely biased Schottky diode, Frenkel-Poole and Schottky emission models are considered [9, 11]. The plot of ln(I R /E) and ln(I R /T 2 ) versus E 1/2 gives the linear curve for the Frenkel-Poole and Schottky emission and the slope can be expressed as fowllowing [11].
Fig. 2

Room—temperature IV and CV curves of ErSi1.7/p-Si diode. The extracted Schottky barrier height for hole is 0.69 and 0.83 V from IV (Φ BP IV ) and CV (Φ BP CV ) method, respectively. In a and b, n and N A  denote ideality factor and doping concentration of substrate, respectively.

Reprinted, with permission, from [10]

$$S = \frac{q}{nkT}\sqrt {\frac{q}{\pi \varepsilon }}$$

where, n = 1, 2 for the case of Frenkel-Poole and Schottky emission, respectively. Here, q is the electron charge quantity, k Boltzmann’s constant, ε permittivity, and E the maximum electric field in Schottky diode. The theoretically calculated slopes at 27 °C for Frenkel-Poole and Schottky emission is 0.0087 and 0.0043 (V/cm)−1/2, respectively.

Figure 3 shows ln(I R /E) and ln(I R /T 2 ) versus E 1/2 curves obtained with the use of IV data shown for the erbium-silicided Schottky diode in Fig. 2a. The slopes as determined from the fit to the data are extracted as 0.013 and 0.027 (V/cm)−1/2, for Frenkel-Poole and Schottky emission, respectively. The experimentally determined slope is slightly larger than the theoretical value for Frenkel-Poole case, but is much larger than the theoretical value for Schottky emission. Thus, the result is more consistent with Frenkel-Poole emission which implies the existence of deep trap level within depletion region of erbium-silicided Schottky diode.
Fig. 3

Electric field dependence of ErSi1.7/p-Si diode in the reverse bias region at 27 °C. The circle and square symbol correspond to the Frenkel-Poole and Schottky emission, respectively

Reprinted, with permission, from [10]

The equivalent circuit of Schottky diode, including the trap states can be modeled as shown as inset of Fig. 4 [9]. In the figure, C D , C t and R t are the semiconductor depletion-layer capacitance, traps associated capacitance and resistance, respectively. The product C t ·R t is defined as the trap lifetimeτ. The parallel branch of the equivalent circuit in Fig. 4 can be converted into a frequency-dependent C p in parallel with a frequency-dependent conductance G p and can be expressed as following [10].
Fig. 4

Frequency versus conductance loss plot. From this plot, the trap density (D t ) and lifetime (τ) can be extracted. The reversely biased voltage is 0.2 V. Inset shows equivalent circuit of Schottky diode including trap states

Reprinted, with permission, from [10]

$$\frac{{G_{p} }}{\omega } = \frac{{C_{t} \omega \tau }}{{1 + \omega^{2} \tau^{2} }},\quad C_{p} = C_{D} + \frac{{C_{t} }}{{1 + \omega^{2} \tau^{2} }}$$
where, ω is the angular frequency.

In (2), the plot of G p versus ωτ goes through maximum when ωτ = 1, and gives τ directly. The value of G p at the maximum is C t /2. Thus, equivalent parallel conductance, divided by angular frequency gives C t and τ directly from the measured conductance. The trap density is obtained by using the relation D t  = C t /qA, where A is the diode area. By using the extracted value C t in G p relation, C D can be extracted directly by using C p . Also, C t andτ can be evaluated by using C p relation. But in this case, inaccuracy of extracted values can exist because of the sensitive dependence of C p to measured frequency, ω. For the consideration of external resistance including substrate and contact resistance, serial connection of additional resistor can be added.

Figure 4 shows the plot of G p versus frequency with the 0.2 V reverse bias condition. The conductance and capacitance are measured using HP4285A impedance analyzer. In figure, the circle and solid line represent measured and fitted data, respectively. From the curve fitting, the extracted C t , D t and τ value are 2.4 × 10−6 Farads/cm2, 1.5 × 1013 traps/cm2 and 3.75 ms, respectively. The extracted C D value is 10.6 × 10−9 Farads/cm2. The extracted interface-trap density is higher compared with the typical values in SiO2 interface [12]. This interface-trap can be cured using hydrogen annealing.

By using the aforementioned method, depletion capacitance (C D ) values are extracted for the various reverse bias conditions. Figure 4 shows the plot of 1/C D 2 versus reverse voltage and open and closed circles represent the as-measured (C P ) and corrected depletion capacitance (C D ) data, respectively. C P includes C t , giving the wrong Schottky barrier height in the plot of 1/C 2 versus reverse voltage. The slope of corrected data has higher values than that of as-measured data because C t is eliminated from C P . From Fig. 5, the re-extracted Schottky barrier height is 0.76 eV for hole and 0.36 eV for electron. The extracted value is consistent with reported photoemission method, which shows the validity of newly developed method [13]. The extracted Schottky barrier height of erbium-silicide is higher compared with the value extracted in SB-MOSFETs results (0.28 eV) [3]. In SB-MOSFETs, image force induced Schottky barrier height lowering is severe due to the electrically induced inversion carriers. At strong inversion condition, the estimated barrier lowering value is almost 0.1 eV [5]. Thus, in SB-MOSFETs, the effective Schottky barrier height can be lower than the value extracted by Schottky diode measurement. Also, when interface traps are considered in Schottky interface, Fermi level pinning effect should be analyzed. The existence of trap states cause the strong pinning of Fermi level of being considered silicide material. For example, the expected Fermi level of erbium is around −3.2 eV which means the zero-Schottky barrier for electron. However, the electrically extracted barrier height of erbium-silicide is around 0.28 eV for electron. Thus, Fermi level pinning and trap state should be carefully controlled. More deep level discussions will be made in another report.
Fig. 5

Re-extraction of Schottky barrier height by eliminating the capacitance associated with trap

Reprinted, with permission, from [10]

3.2 Scalability of SB-MOSFETs

Figure 6 shows IDS-VGS characteristics of the 20 μm long channel n/p-type SB-MOSFETs. The gate oxide and spacer thickness is 5 and 15 nm, respectively. Both the n/p-type SB-MOSFETs show high on/off current ratio, larger than Ion/Ioff > 105 with low leakage current (ILKG < 100 pA/μm). The on/off ratio and the leakage current level is the highest and lowest values compared with previously published data in n-type SB-MOSFETs [6]. Also, DIBL is almost suppressed in both n/p-type SB-MOSFETs and the SS value is 60 mV/decade in n-type SB-MOSFETs.
Fig. 6

IDS-VGS (a) and IDS-VDS (b) characteristics of 20 μm long channel n/p-type SB-MOSFET

Reprinted, with permission, from [15]

Figure 7 shows the IDS-VGS characteristics of erbium-silicided 100 nm gate length n/p-type SB-MOSFETs. Also, this 100 nm gate length n/p-type SB-MOSFET shows excellent short channel characteristics. The measured SS and DIBL values are 70 mV/decade and 30 mV, respectively, for n-type SB-MOSFETs.
Fig. 7

IDS-VGS (a) and IDS-VDS (b) characteristics of 100 nm gate length n/p-type SB-MOSFET

Reprinted, with permission, from [15]

Figure 8 shows the SEM image and electrical IDS-VGS characteristics of 23 nm gate length n-type SB-MOSFETs [15]. Although the substrate boron doping concentration is 1015 cm−3, short channel effect is sufficiently suppressed due to the existence of Schottky barrier between source and channel. The existence of interface traps can severely affect the short channel characteristics in SB-MOSFETs, especially for the low doped substrate case due to the severe penetration of drain field into the source/channel interface. The penetration of drain field can cause the interface trap mediated leakage current, giving the degradation of SS value and leakage current characteristics.
Fig. 8

SEM image and IDS-VGS characteristics of 23 nm n-type SB-MOSFET

Reprinted, with permission, from [15]

Figure 9 shows the DIBL (a) and SS (b) characteristics of SB-MOSFETs with the variation of gate length. In Fig. 8a, solid and dotted line represents theoretical DIBL characteristics of SB-MOSFETs and DG-MOSFETs, respectively and the open circles are plotted from the published data [6] and the closed circles are the data from this work. The scaling theory of DG-MOSFETs can be found in [14]. In the calculations of DIBL in DG-MOSFETs, gate oxide and body thickness are assumed as 1 and 10 nm, respectively. Note that these assumed values correspond to the ultimate minimum values in device technology. The DIBL characteristics of SB-MOSFETs are better than DG-MOSFETs. The reason for this is due to the existence of the Schottky barrier between source and channel. This is explained in Fig. 10. In DG-MOSFETs, the subthreshold characteristics, including DIBL and SS, are mainly determined by the built-in potential. In short channel device, as the drain voltage increases, built-in potential between source and channel decreases, giving DIBL effect. But in SB-MOSFETs, the subthreshold characteristics are mainly determined by the Schottky barrier. Thus DIBL characteristics of SB-MOSFETs can be described by the Schottky barrier lowering due to the drain voltage. In SB-MOSFETs, the decrease of threshold voltage with the increase of drain voltage, due to the Schottky barrier lowering, can be expressed as following.
Fig. 9

DIBL (a) and subthreshold swing (b) characteristics of SB-MOSFETs

Fig. 10

Different DIBL mechanisms in MOSFETs (a) and SB-MOSFETs (b)

$$\Updelta {\text{V}}_{\text{T}} = \sqrt {\frac{q}{4\pi \varepsilon }} \left[ {\sqrt {\frac{{V_{DS}^{H} }}{{L_{eff} }}} - \sqrt {\frac{{V_{DS}^{L} }}{{L_{eff} }}} } \right]$$
where, L eff means the effective gate length and V DS H and V DS L means high and low drain voltage, respectively.

In Fig. 9b, dotted line represents theoretical SS characteristics of DG-MOSFETs, with 1 nm gate oxide and 10 nm body thickness. As shown, the SS characteristics of SB-MOSFETs are almost compatible with ultimately scaled DG-MOSFETs. However there exist deviations of DIBL values of SB-MOSFETs from the theoretical prediction. The reason for these deviations are due to the interface trap states between silicon and silicide interface. As analyzed in Fig. 3, most of the trap states contribute to Frenkel-Poole emission which causes the degradation of DIBL and also SS characteristics in SB-MOSFETs. Thus, the control of the interface trap states in SB-MOSFETs are the important key factor for the improvement of DIBL and SS characteristics. One efficient method for the reduction of interface traps is N2 annealing and the detailed method and the results are reported in [15].

4 Conclusion

Erbium-silicided Schottky diode is fabricated on the p-type silicon and the electrical characteristics is analyzed using the IV and CV measurement methods. From IV analysis, the major leakage current conduction mechanism of reversely biased Schottky diode is due to the Frenkel-Poole emission originating from the existence of deep trap level in the depletion region of erbium-silicided Schottky diode. The trap density and lifetime are evaluated using equivalent circuit modeling method and the extracted trap density and lifetime are 1.5 × 1013 traps/cm2 and 3.75 ms, respectively. The corrected Schottky barrier height (0.76 eV) is extracted by eliminating the parallel connected capacitance associated with trap using equivalent circuit modeling method. Also, SB-MOSFETs are manufactured and the electrical characteristics are analyzed. In SB-MOSFETs, DIBL is strongly suppressed due to the existence of Schottky barrier between source and channel. DIBL and SS characteristics of SB-MOSFETs are compatible with the ultimately scaled DG-MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime as the alternative to the MOSFETs.



This work was supported by the National Research Foundation of Korea(NRF) Grant funded by the Korean government(MSIP) (NRF-2015R1A4A1041631).

Competing interests

The author declares that he has no competing interests.

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Authors’ Affiliations

Department of Materials Science and Engineering, Hallym University


  1. T. Chu, H. Ilatikhameneh, G. Klimeck, R. Rahman, Z. Chen, Electrically tunable bandgaps in bilayer MoS2. Nano. Lett. 15, 8000–8007 (2015)View ArticleGoogle Scholar
  2. H. Yang, J. Heo, S. Park, H. Song, D.H. Seo, K. Byun, P. Kim, I. Yoo, H. Chung, K. Kim, Graphene barrister, a triode device with a gate-controlled Schottky barrier. Science. 336, 1140–1143 (2012)View ArticleGoogle Scholar
  3. F. Xia, D.B. Farmer, Y. Lin, P. Avouris, Graphene field-effect transistors with high on/off current ratio and large transport band gap at room temperature. Nano. Lett. 10, 715–718 (2010)View ArticleGoogle Scholar
  4. S. Zhu, J. Chen, M.-F. Li, S.J. Lee, J. Singh, C.X. Zhu, A. Du, C.H. Tung, A. Chin, D.L. Kwong, N-type Schottky barrier source/drain MOSFET using ytterbium silicide. IEEE. Electron. Device. Lett. 25, 565–567 (2004)View ArticleGoogle Scholar
  5. M. Jang, Y. Kim, J. Shin, S. Lee, A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor. Appl. Phys. Lett. 84, 741–743 (2004)View ArticleGoogle Scholar
  6. J. Kedzierski, P. Xuan, E. K. Erik, H. Anderson, J. Bokor, T.-J. King, C. Hu, Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime, IEDM. Tech. Dig. 57–60 (2000)Google Scholar
  7. R.T. Tung, Electron transport at metal-semiconductor interfaces: general theory. Phys. Rev. B. 45, 13509–13523 (1992)View ArticleGoogle Scholar
  8. R.B. Darling, Current-voltage characteristics of Schottky barrier diodes with dynamic interfacial defect state occupancy. IEEE. Trans. Electron. Devices. 43, 1153–1160 (1996)View ArticleGoogle Scholar
  9. S.M. Sze, Physics of semiconductor devices (Wiley, New York, 1981), pp. 379–390Google Scholar
  10. M. Jang, Y. Kim, J. Shin, S. Lee, Characterization of Erbium-silicided Schottky diode junction. IEEE. Elect. Dev. Lett. 26, 354–356 (2005)View ArticleGoogle Scholar
  11. H.D. Lee, Characterization of shallow silicided junctions for sub-quarter micron ULSI technology—extraction of silicidation induced Schottky contact area. IEEE. Trans. Electron. Devices. 47, 762–767 (2000)View ArticleGoogle Scholar
  12. V. Sonnenberg, J.A. Martino, Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction. Solid-State. Electron. 43, 2191–2199 (1999)View ArticleGoogle Scholar
  13. M. Jang, K. Kang, S. Lee, K. Park, Simulation of Schottky barrier tunnel transistor using simple boundary condition. Appl. Phys. Lett. 82, 2718–2720 (2003)View ArticleGoogle Scholar
  14. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto, Scaling theory for double-gate SOI MOSFET’s’. IEEE. Trans. Elect. Dev. 40, 2326 (1993)View ArticleGoogle Scholar
  15. M. Jang, Y. Kim, M. Jeon, C. Choi, I. Baek, S. Lee, B. Park, N2-annealing effects on characteristics of Schottky-barrier MOSFETs. IEEE. Trans. Elect. Dev. 53, 1821–1825 (2006)View ArticleGoogle Scholar


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