Effect of ribbon width on electrical transport properties of graphene nanoribbons
- Kyuhyun Bang†1,
- Sang-Soo Chee†2,
- Kangmi Kim2,
- Myungwoo Son2,
- Hanbyeol Jang2,
- Byoung Hun Lee2,
- Kwang Hyeon Baik3,
- Jae-Min Myoung1Email author and
- Moon-Ho Ham2Email authorView ORCID ID profile
© The Author(s) 2018
Received: 28 January 2018
Accepted: 27 February 2018
Published: 15 March 2018
There has been growing interest in developing nanoelectronic devices based on graphene because of its superior electrical properties. In particular, patterning graphene into a nanoribbon can open a bandgap that can be tuned by changing the ribbon width, imparting semiconducting properties. In this study, we report the effect of ribbon width on electrical transport properties of graphene nanoribbons (GNRs). Monolayer graphene sheets and Si nanowires (NWs) were prepared by chemical vapor deposition and a combination of nanosphere lithography and metal-assisted electroless etching from a Si wafer, respectively. Back-gated GNR field-effect transistors were fabricated on a heavily p-doped Si substrate coated with a 300 nm-thick SiO2 layer, by O2 reactive ion etching of graphene sheets using etch masks based on Si NWs aligned on the graphene between the two electrodes by a dielectrophoresis method. This resulted in GNRs with various widths in a highly controllable manner, where the on/off current ratio was inversely proportional to ribbon width. The field-effect mobility decreased with decreasing GNR widths due to carrier scattering at the GNR edges. These results demonstrate the formation of a bandgap in GNRs due to enhanced carrier confinement in the transverse direction and edge effects when the GNR width is reduced.
Over the past decade, graphene has emerged as a promising candidate for application in future nanoelectronics due to its excellent material properties such as high carrier mobility, excellent mechanical flexibility, high thermal conductivity, and high optical transparency [1–7]. In particular, graphene is regarded as an outstanding channel material because of its electron mobility as high as 200,000 cm2 V−1 s−1 . In spite of the superior properties of graphene, there are several challenges to be overcome for practical applications in electronic devices.
As graphene is intrinsically a semimetal with zero bandgap, the formation of a bandgap is necessary to achieve a sufficiently high on/off current ratio when used as a channel in a field-effect transistor (FET). Several routes to bandgap tuning in graphene have been reported, such as chemical doping of graphene, application of a vertical electric field in bilayer graphene, and patterning graphene into a narrow ribbon structure [9–11]. Among these, patterning graphene into nanoribbons can open a bandgap that is tunable by narrowing the ribbon width to less than 50 nm. Graphene nanoribbons (GNRs), which are narrow strips of graphene, exhibit semiconducting properties due to the quantum confinement and edge effects. Han et al. experimentally demonstrated that the energy bandgap of GNRs scale inversely with the channel width . Wang et al. also reported a high on/off current ratio of up to ~ 104 in GNR FETs with sub-5 nm widths at room temperature . The fabrication methods for GNRs include e-beam lithography [12–15], block copolymer lithography , and use of a nanowire (NW) etch mask [17–19] on graphene sheets, and also through unzipping of carbon nanotubes [20–24]. In this study, we investigated the ribbon-width dependence of electrical transport properties of GNRs. Si NWs, fabricated by a combination of polystyrene (PS) nanosphere lithography and metal-assisted electroless etching, were used as etch masks to fabricate a nanoribbon structure by exposing graphene to oxygen plasma. The Si NWs were aligned on the graphene between the two electrodes by electric-field-assisted assembly, and oxygen plasma was used to transfer NW morphology onto the graphene by removing unprotected graphene. The ribbon widths of the GNRs were controlled by the diameters of the Si NWs, and the electrical transport properties of these GNRs with different ribbon widths were investigated.
2.1 Synthesis and transfer of monolayer graphene
Cu foil (Alfa Aesar) was used as a substrate for graphene growth. The Cu foil was annealed at 1000 °C for 30 min under 10 sccm of H2 gas flow to increase the Cu grain size and ensure the removal of native oxide and a smooth Cu surface. Graphene was grown on Cu foil at 1000 °C using a mixture of 20 sccm of CH4 and 50 sccm of H2 by low-pressure chemical vapor deposition (CVD) [16, 25]. To prepare for the graphene transfer to a Si/SiO2 substrate, the surface of the graphene on Cu was coated with poly(methyl methacrylate) (PMMA, MicroChem) as a transfer medium. The PMMA-coated samples were baked at 60 °C for 5 min. The Cu was wet-etched using a copper etchant (CE-100, Transene Co., Inc.), resulting in graphene/PMMA films floating on the etchant. These films were then collected onto Si/SiO2 substrates, and the PMMA layers were removed with acetone, yielding Si/SiO2/graphene.
2.2 Fabrication of Si NWs with different diameters
Si NWs were prepared by nanosphere lithography, which is a technique for generating hexagonally close-packed nanoscale patterns of nanometer-sized PS spheres on a Si wafer. PS beads with different diameters of 100, 300, and 460 nm were dispersed in methanol with Triton X-100 as a surfactant. To make the surface of the Si substrate hydrophilic, the substrate was immersed in a piranha solution (1:3 of 30% H2O2:H2SO4) at 100 °C. Then, the substrate was rinsed with deionized water and spin-coated with the PS bead suspension at 3000 rpm to form a monolayer of PS beads on the Si substrate. The large-area ordered and close-packed monolayer assembly of PS beads on the Si substrate was transformed into a non-close-packed arrangement by reducing the diameter of the PS spheres using O2 reactive ion etching (RIE). The e-beam evaporator was used to deposit 40 nm-thick Ag films as catalysts to form Si NWs from the substrate, and the substrate was subsequently sonicated in chloroform for 20 min to remove the PS spheres. Wet etching was performed at 50 °C in a solution of 4.5 M HF and 0.5 M H2O2 for 20–30 min, yielding vertically aligned Si NW arrays. Finally, the Ag films were removed by immersion in boiling aqua regia (3:1 of HCl:HNO3) at 100 °C for 20 min.
2.3 Fabrication of GNR FETs
A large-area monolayer graphene on a heavily p-doped Si substrate (bottom gate) coated with a 300 nm-thick SiO2 layer (gate dielectric) was used as a starting material to fabricate GNR FETs. First, the source/drain pads were patterned by photolithography, followed by deposition of Ti/Au as the electrode metal on the graphene by e-beam evaporation. The channel length of the FETs was 8 μm. The Si NWs were raked out from the vertically aligned Si NW arrays prepared on the Si substrate and dissolved in isopropyl alcohol (IPA). This Si NW suspension was sonicated for 10 min and centrifuged at 2500 rpm for 10 min. Then, the Si NWs were aligned on graphene between the two electrodes by a dielectrophoresis method. The assembly of Si NWs was performed by dispensing a dilute suspension of the Si NWs onto the substrates with applied voltages of ± 10 V at frequencies of 1–100 kHz (81110A, Agilent Technologies). O2 plasma etching was used to selectively etch an unprotected graphene region away and leave a ribbon structure of graphene underneath the Si NW mask, leading to the formation of GNRs. After that, the NW mask was removed by sonication in IPA, resulting in GNR FETs.
The monolayer graphene was characterized by Raman spectroscopy (LabRAM HR Evolution, Horiba Jovin-Yvon) using a laser with an excitation wavelength of 532 nm. The morphological properties of graphene, Si NWs, and GNRs were investigated by optical microscopy (BX51, Olympus), field-emission scanning electron microscopy (FESEM, JSM-7500F, JEOL), and atomic force microscopy (AFM, XE-100, Park Systems). The electrical characteristics of the GNR FETs were studied with a semiconductor parameter analyzer (E5270B, Agilent Technologies).
3 Results and discussion
In summary, GNRs with different widths were fabricated in a highly controllable manner, and their electrical transport properties were investigated. The GNRs were prepared from CVD-grown graphene sheets by using etch masks based on Si NWs synthesized from Si substrates by a combination of nanosphere lithography and metal-assisted chemical etching, and aligned between two electrodes by an electric-field-assisted alignment method, producing GNR FETs. The ribbon widths of the GNRs were controlled by changing the diameters of the Si NWs and the graphene etching times. The electrical transport characteristics of GNRs were found to be highly dependent on the GNR width: (1) the on/off current ratio was inversely proportional to GNR width; (2) the electrical properties of the GNR FETs showed a strong temperature dependence of the IDS–VGS curves on ribbon width; (3) the field-effect mobility decreased with decreasing width of the GNR; and (4) the bandgap increased with increasing on/off current ratio by narrowing the width of the GNR. These results demonstrate the opening of the bandgap in graphene due to enhanced carrier confinement in the transverse direction and the edge effect in the ribbon structure.
KB and SSC contributed equally to this work. All authors have contributed to conducting experiments and writing the manuscript. All authors read and approved the final manuscript.
The authors declare that they have no competing interests.
This work was supported by Creative Materials Discovery Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (2017M3D1A1040828), Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2015R1D1A1A01058982), Nano Material Technology Development Program of the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (2016M3A7B4909942), the Future Semiconductor Device Technology Development Program (10044868) funded by Ministry of Trade, Industry & Energy (MOTIE) and Korea Semiconductor Research Consortium (KSRC), and Global Frontier R&D Program through the Global Frontier Hybrid Interface Materials (GFHIM) of the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2013M3A6B1078873).
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