Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs)
© The Author(s) 2016
Received: 9 March 2016
Accepted: 2 May 2016
Published: 15 June 2016
The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal–oxide–semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high-k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high-k etching process.
The steady scaling-down of semiconductor device with rapid progress of fabrication technology facilitated high-integration, high-performance . However, scaling-down resulted in short channel effects and power consumption increased exponentially [2, 3]. Recently, low power consumption becomes one of the most important requirements as scaling-down in semiconductor industry with the rapid growth of mobile market.
Thus, many novel devices have been proposed recently to overcome fundamental limit. They include impact-ionization MOS devices [5, 6], nano-electro-mechanical FETs , and tunneling field-effect transistor (TFET) [8–23]. Among them, a TFET is considered one of the most promising candidates for ultra-low-power semiconductor device. TFETs show low I off and sub-60 mV/dec SS at room temperature because electron flows are controlled by band-to-band tunneling mechanism. In addition, TFETs are less influenced by short channel effects than MOSFETs [14, 15] and complementary metal-oxide semiconductor (CMOS) process compatible. On the other hand, TFETs have disadvantages such as lower on current (I on) and ambipolar behavior [16, 17]. To overcome these problems, many studies have been reported by introducing various materials and device structures [17–23].
In this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated. HG TFETs show higher I on, lower ambipolar current (I amb) and smaller SS than conventional TFETs by replacing source-side gate insulator with high-k materials . First, the theoretical background of TFETs and device concepts of HG TFETs will be covered. In addition, HG TFET design was optimized and improved through the simulation. As a result, HG TFETs showed higher performance than that of conventional TFETs. To improve the performance of HG TFETs, improved fabrication methods were proposed. Etching the gate insulator at the source side by using HF vapor improved enlargement of etched gate insulator thickness. In addition, structure of sidewall spacers was changed to remove the high-k layer on the source region by high-k etching process. This solved the problem that tunneling barrier width was increased by fringe field. After the overall process flow for the fabricating HG TFETs using standard CMOS process was introduced, electrical characteristic results of fabricated device demonstrated the simulation results. Proposed HG TFETs showed higher performance than our previous results. As a result, it is concluded that HG TFETs are promising to be used for highly energy efficient ICs.
2 Theoretical studies
2.1 Basic operations of TFETs
2.2 Characteristics of HG TFETs
Device parameters used for simulation
L G (nm)
t SOI (nm)
t ins (nm)
Source/drain doping conc. (cm−3)
Channel doping conc. (cm−3)
L high-k (nm)
k value of high-k dielectric
2.3 Optimization of the device design
2.4 Improvement in device design
Our previous work showed worse HG TFET performance than expected . It was concluded that this result came from some factors: gradual doping profile, enlarged high-k dielectric thickness at the source side and sidewall spacer structures. All of these factors are related to the fabrication process and these have been investigated to improve the performance of HG TFETs.
First, abrupt doping profile at the tunneling junction is very important for TFETs because it determines W tun and electric field which control the tunneling current. Doping profile which is especially overlapped by high-k material has an influence on HG TFETs because performance of HG TFETs is mostly determined by formation of a local minimum of the E c at the tunneling junction . As a result, abrupt doping profiles at the tunneling junction are suitable for higher I on and lower SS. However, gradual doping profiles are applied to our HG TFETs because we used conventional RTA instead of advanced annealing method. Thus, fabrication conditions which control the doping profile should be optimized. In general, doping profiles at the tunneling junction are influenced by the spacer length (L spacer) and the RTA time (T RTA). L spacer is the sum of an inner high-k spacer length and an outer low-k spacer length. To adopt the fabrication conditions, two-dimensional semiconductor process simulation and device simulation has been performed by using Silvaco ATHENA and ATLAS . In the case of process simulation, some conditions were changed from the conditions used for device simulation. Abrupt doping profile is changed to gradual doping profile which is determined by T RTA.
Second, high-k dielectric partially located at the source side increase the gate-to-channel coupling strength and this leads to the particular energy band structure . HG TFETs show lower SS and higher I on because of a local minimum of the E c at the tunneling region. Though the thickness of high-k dielectric should be equal to T ox, this is enlarged during etch process of SiO2 gate insulator. Thus, the difference of the gate-to-channel coupling strength between channel regions overlapped by the high-k dielectric and SiO2 decreased. It degrades the performance of HG TFETs and solution to this will be discussed in chapter 3.
Figure 13b shows extracted I on as a function of L spacer and T RTA. The turn-on voltage (V turn-on) is defined as V G when I D is 10 fA/μm. I on is defined as I D when V D is 0.7 V and V G is 0.7 V higher than V turn-on. I on shows similar tendency observed in SS as a function of L spacer and T RTA. Optimum L spacer increases as T RTA increases for the same reason. Tunneling current increases as electric field at the tunneling region increases and it is reversely exponential to W tun. Electric field is determined by the slope of the energy level in the band diagrams and W tun is also strongly influenced by doping profiles. Mostly optimized I on is shown when T RTA is 3 s because more abrupt doping profile is formed as T RTA decreases. When T RTA is 3 s, optimum L spacer is 24 nm as same as in the case of SS.
From the results of simulation, overlapped region between Fig. 13a, b is selected as the target for the fabrication condition. Finally, optimized L spacer is 24 nm and T RTA is 3 s. Though there is variability from the fabrication conditions, it would be within the margin of error because SS shows little change.
3 Fabrication of HG TFETs and analysis
3.1 Improvement in fabrication methods
As discussed in chapter 2, performance degradation was shown for previous HG TFETs and reasons are closely related to fabrication issues. Gradual doping profile is one of them and it is difficult to be improved because it needs advanced annealing equipments. However, there are solutions for enlarged high-k dielectric thickness at the source side and the structure of the sidewall spacer. Two key ideas have been introduced to enhance the performance of HG TFETs in this work.
Additionally, process for formation of the HG structure has been changed to remove the high-k dielectric layer on the source region. In previous work, outer TEOS spacers were formed right after HfO2 ALD process and then residual HfO2 was removed. As a result, HfO2 layers were remained under TEOS spacers and this decreased energy band of the source region because of increased fringe field from the gate when gate bias is applied . This led to increase of W tun and degraded performance of HG TFETs. This problem has been improved by etching HfO2 layers before TEOS spacers were formed. In this case, anisotropic HfO2 etching process should be defined to protect the HfO2 layer inserted under the gate. Thus, inductively coupled plasma (ICP) dry etcher was used to etch HfO2 layer on the source region. Adjusting etching time is very important because HfO2 layer on the source region should be removed and HfO2 layer under the gate should be protected at the same time. In addition, very careful control of HfO2 dry etch process was needed because silicon under the HfO2 layerrewis also etched well by HfO2 etch process condition (BCl3 100 sccm, 700 W, 5 Wb, 10 mtorr). As a result, HfO2 layers on the source region were removed and 3-nm inner HfO2 spacers were remained finally.
3.2 Device fabrication
3.3 Electrical characteristics
Electrical characteristics summarization of proposed HG TFET compared with previous HG TFET and SiO2-only TFET
Proposed HG TFET
Previous HG TFET
L G (μm)
W G (μm)
T ox (nm)
V DD (V)
I on (nA/μm)
I min (pA/μm)
I on/I off
5.6 × 104
1.8 × 104
3.5 × 10
Although HG TFETs are proposed for low-power application, SS of HG TFETs is larger than 60 mV/dec and current drivability is much smaller than requirements of the Low Standby Power devices . First of all, abrupt doping profile is necessary for higher I on and lower SS. Because conventional RTA is used in this work, W tun is increased and it is difficult to control the tunneling junction. Advanced annealing methods such as spike or laser annealing can be considered for this purpose [23, 32]. In addition, tunneling current can be enhanced by using lower bandgap semiconductors such as SiGe, Ge and III-V materials [17, 19–21]. If relative permittivity of high-k material increases, performance of HG TFETs would be further improved.
In this work, HG TFETs have been investigated through the simulation and fabrication of devices in order to demonstrate the higher performance and low-power consumption. Optimized HG TFETs showed higher I on and, lower I amb and SS than conventional TFETs by replacing source-side gate insulator with a high-k material. A high-k material partially located at the source side induced a local minimum of E c due to relative permittivity discrepancy between high-k dielectric and SiO2 layer. In addition, proposed HG TFETs showed improved device performance than previous HG TFETs by improvement in device design. For the fabrication of HG TFETs with improved performance, key processes were modified. HF vapor was used to etch the source-side gate insulator uniformly and HfO2 etch was performed right after HfO2 ALD to remove the HfO2 layer remained on the source region. Through the electrical test of fabricated devices, proposed HG TFETs showed higher performance than previous HG TFETs and conventional TFETs in terms of I on and SS. To sum up, it is promising that HG TFETs are alternative devices which will complement the MOSFETs for highly energy efficient ICs.
All authors have contributed to the writing of the manuscript. Both authors read and approved the final manuscript.
This work was supported in part by the NRF of Korea funded by the MSIP under Grant NRF-2015003565 (Mid-Career Researcher Program), NRF-2015046617 (Fundamental Technology Program) and in part by the MOTIE/KSRC under Grant 10044842 (Future Semiconductor Device Technology Development Program).
The authors declare that they have no competing interests.
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- M. Bohr, The new era of scaling in an SoC world, in IEEE International Solid-State Circuits Conference (ISSCC) (2009), pp. 23–28Google Scholar
- D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, H.-S.P. Wong, Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3), 259–288 (2001)View ArticleGoogle Scholar
- L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, T.-J. King, Extremely scaled silicon nano-CMOS devices. Proc. IEEE 91(11), 1860–1873 (2003)View ArticleGoogle Scholar
- Y. Taur, E. Nowak, CMOS devices below 0.1 μm: how high will performance go? in IEEE International Electron Devices Meeting (IEDM) Technical Digest (1997), pp. 215–218Google Scholar
- K. Gopalakrishnan, P. B. Griffin, J. D. Plummer, I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q, in IEEE International Electron Devices Meeting (IEDM) Technical Digest (2002), pp. 289–292Google Scholar
- W.Y. Choi, J.Y. Song, J.D. Lee, Y.J. Park, B.-G. Park, 100-nm n-/p-channel I-MOS using a novel self-aligned structure. IEEE Electron Device Lett. 26(4), 261–263 (2005)View ArticleGoogle Scholar
- H. Kam, D.T. Lee, R.T. Howe, T.J. King, A new nano-electromechanical field effect transistor (NEMFET) design for low-power electronics, in IEEE International Electron Devices Meeting (IEDM) Technical Digest (2005), pp. 463–466Google Scholar
- P.-F. Wang, K. Hilsenbeck, Th Nirschl, M. Oswald, C. Stepper, M. Weiss, D. Schmitt-Landsiedel, W. Hansch, Complementary tunneling transistor for low power application. Solid-State Electron. 48(12), 2281–2286 (2004)View ArticleGoogle Scholar
- T. Nirschl, P.-F. Wang, C. Weber, J. Sedlmeir, R. Heinrich, R. Kakoshke, K. Schrufer, J. Holz, C. Pacha, T. Schulz, M. Ostermayr, A. Olbrich, G. Georgakos, E. Ruderer, W. Hansch, D. Schmitt-Landsiedel, The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes, in IEEE International Electron Devices Meeting (IEDM) Technical Digest, (2004), pp. 195–198Google Scholar
- Q. Zhang, W. Zhao, A. Seabaugh, Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 27(4), 297–300 (2006)View ArticleGoogle Scholar
- W.Y. Choi, B.-G. Park, J.D. Lee, T.-J.K. Liu, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett. 28(8), 743–745 (2007)View ArticleGoogle Scholar
- R. Gandhi, Z. Chen, N. Singh, K. Banerjee, S. Lee, Vertical Si-nanowire n-type tunneling FETs with low subthreshold swing (≤50 mV/decade) at room temperature. IEEE Electron Device Lett. 32(4), 437–439 (2011)View ArticleGoogle Scholar
- J. Appenzeller, Y.-M. Lin, J. Knoch, P. Avouris, Band-to-band tunneling in carbon nanotube field-effect transistors. Phys. Rev. Lett. 93(19), 196805 (2004)View ArticleGoogle Scholar
- K. Boucart, A.M. Ionescu, Length scaling of the double gate tunnel FET with a high-k dielectric. Solid-State Electron. 51(11–12), 1500–1507 (2007)View ArticleGoogle Scholar
- J. Knoch, S. Mantl, J. Appenzeller, Impact of the dimensionality on the performance of tunneling FETs: bulk versus one-dimensional devices. Solid-State Electron. 51(4), 572–578 (2007)View ArticleGoogle Scholar
- J.-S. Jang, W.Y. Choi, Ambipolarity factor of tunneling field-effect transistors (TFETs). J. Semicond. Technol. Sci. 11(4), 272–277 (2011)View ArticleGoogle Scholar
- T. Krishnamohan, D. Kim, S. Raghunathan, K. Saraswat, Double gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope, in IEEE International Electron Devices Meeting (IEDM) Techical Digest (2008), pp. 947–949Google Scholar
- W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans. Electron Devices 57(9), 2317–2319 (2010)View ArticleGoogle Scholar
- S.H. Kim, H. Kam, C. Hu, T.-J. K. Liu, Germanium-source tunnel field effect transistors with record high ION/IOFF, in VLSI Symposium Technical Digest, 2009 (2009), pp. 178–179Google Scholar
- G. Zhou, Y. Lu, R. Li, Q. Zhang, W.S. Hwang, Q. Liu, T. Vasen, C. Chen, H. Zhu, J.-M. Kuo, S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, H. Xing, Vertical InGaAs/InP tunnel FETs with tunneling normal to the gate. IEEE Electron Device Lett. 32(11), 1516–1518 (2011)View ArticleGoogle Scholar
- K. E. Moselund, H. Ghoneim, M. T. Bjork, H. Schmid, S. Karg, E. Lortscher, W. Riess, H. Riel, Comparison of VLS grown Si NW tunnel FETs with different gate stacks, in Proceedings of the European Solid-State Device Research Conference (ESSDERC) (2009), pp. 448–451Google Scholar
- F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B. Previtali, S. Deleonibus, Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance, in IEEE International Electron Devices Meeting (IEDM) Technical Digest (2008), pp. 163–166Google Scholar
- R. Jhaveri, V. Nagavarapu, J.C.S. Woo, Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor. IEEE Trans. Electron Devices 58(1), 80–86 (2011)View ArticleGoogle Scholar
- SILVACO International, Santa Clara, CA 95054, USA, ATHENA/ATLAS User’s Manual (2012)Google Scholar
- G. Lee, W.Y. Choi, Low-power circuit applicability of hetero-gate-dielectric tunneling field-effect transistors. IEICE Trans. Electron. E95-C(5), 910–913 (2012)View ArticleGoogle Scholar
- M.J. Lee, W.Y. Choi, Effect of device geometry on hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). IEEE Electron Device Lett. 33(10), 1459–1461 (2012)View ArticleGoogle Scholar
- G. Lee, W.Y. Choi, Dual-dielectric-constant spacer hetero-gate-dielectric tunneling field-effect transistors. Semicond. Sci. Technol. 28, 052001 (2013)View ArticleGoogle Scholar
- H.G. Virani, R.B.R. Adari, A. Kottantharayil, Dual-k spacer device architecture for the improvement of performance of Silicon n-channel tunnel TFETs. IEEE Trans. Electron Devices 57(10), 2410–2417 (2010)View ArticleGoogle Scholar
- A. Chattopadhyay, A. Mallik, Impact of a spacer dielectric and a gate overlap/underlap on the device performance of a tunnel field-effect transistors. IEEE Trans. Electron Devices 58(3), 677–683 (2011)View ArticleGoogle Scholar
- W. Lee, W.Y. Choi, Influence of inversion layer on tunneling field-effect transistors. IEEE Electron Device Lett. 32(9), 1191–1193 (2011)View ArticleGoogle Scholar
- The International Technology Roadmap for Semiconductors (ITRS) (2012), http://www.itrs2.net/. Accessed 6 Jan 2016
- D. Leonelli, A. Vandooren, R. Rooyackers, S.D. Gendt, M.M. Heyns, G. Groeseneken, Drive current enhancement in p-tunnel FETs by optimization of the process conditions. Solid-State Electron. 65–66, 28–32 (2011)View ArticleGoogle Scholar