Accurate extraction of WSe2 FETs parameters by using pulsed I-V method at various temperatures
© The Author(s) 2016
Received: 9 August 2016
Accepted: 17 October 2016
Published: 21 November 2016
This work investigates the intrinsic characteristics of multilayer WSe2 field effect transistors (FETs) by analysing Pulsed I-V (PIV) and DC characteristics measured at various temperatures. In DC measurement, unwanted charge trapping due to the gate bias stress results in I-V curves different from the intrinsic characteristic. However, PIV reduces the effect of gate bias stress so that intrinsic characteristic of WSe2 FETs is obtained. The parameters such as hysteresis, field effect mobility (μeff), subthreshold slope (SS), and threshold voltage (V th) measured by PIV are significantly different from those obtained by DC measurement. In PIV results, the hysteresis is considerably reduced compared with DC measurement, because the charge trapping effect is significantly reduced. With increasing temperature, the field effect mobility (μeff) and subthreshold swing (SS) are deteriorated, and threshold voltage (V th) decreases.
Two-dimensional(2D) layered materials such as graphene and boron nitride offer new opportunities in the field of electronics with its excellent physical, chemical properties [1–6]. Though graphene has been studied most widely, its lack of bandgap limits its application. Transition metal dichalcogenides (TMDCs) provide a solution to this problem with their sizable bandgap energy and ultra-thin form of layers. Among them, WSe2 FETs can be very appealing for the nanoscale electronic applications and blackplanes for flat panel display (FPD) due to their high mobility (~100 cm2/V·s), excellent on/off ratio(~107), and low subthreshold swing (SS, ~70 mV/decade) [7–9].
When we simulate the circuits which consist of WSe2 FETs, it is necessary to know the parameters of the FETs. Most of the parameters reported up to now were extracted from the I-V characteristics obtained by the DC method. However, these values were not correct, because a large hysteresis is observed due to the gate bias stress during the DC measurement [10–12]. On the other hand, in the Pulsed I-V (PIV) measurement, the effect of gate bias stress is reduced greatly so that intrinsic characteristic of WSe2 FETs can be obtained [13, 14]. Thus PIV method is considered as a reasonable method for estimating the performance and reliability of semiconductor devices. The purpose of PIV method is to avoid the negative effects such as self-heating and transient trapped charges. Therefore, the PIV method can provide the accurate device parameters needed for improved computer-aided-engineering (CAE) software models. However, there have been no reports on the parameter extraction from the fabricated WSe2 FETs at various temperatures. In this work, we show the I-V curves measured by PIV and DC measurement methods, and compare the parameters extracted from the results obtained by both methods at various temperatures (−30 to 40 °C).
2 Experimental details
3 Result and discussion
In addition, as the temperature rises, the difference between the mobility measured by DC forward and reverse scans increases as shown in Fig. 5b. The reason for the difference is explained as follows. Compared to the case of the forward scan, the holes in the reverse scan are increasingly emitted to the valence band with increasing temperature since increasing temperature increases the energy of the holes trapped.
SS measured by DC measurement is greater than SS measured by PIV, because charge trapping decreases the current in DC measurement which makes SS larger. Furthermore, SS measured by DC forward scan is larger than the SS measured by DC reverse scan, because as explained above the slope of DC forward scan is smaller than that of DC reverse scan. The difference between SS measured by DC forward scan and SS measured by DC reverse scan increases as temperature rises. This phenomenon can be explained by the physics explained in the mobility difference with the temperature.
The threshold voltage (V th) was calculated by reading a gate-source voltage (V GS) at a constant current (I d = 10−8 A). In PIV method, the threshold voltage shifts to the positive direction due to the increase of thermally activated carrier density. At any temperature, the threshold voltage measured by DC forward scan is in the rightmost position, and the threshold voltage measured by DC reverse scan is in the leftmost position. The reason can be explained as follows. During DC forward scan, the electron was trapped before V GS reaches V th so the threshold voltage moves to the right. On the other hand, during DC reverse scan, the hole was trapped before V GS reaches V th so the threshold voltage moves to the left. Furthermore, the difference between V ths measured by DC forward and reverse scans increases with increasing temperature, since the hysteresis increases.
In this paper, we extracted key parameters of WSe2 FETs accurately at various temperatures by adopting pulsed I-V (PIV) method. The behavior of these parameters are different from that of the parameters obtained by DC method. For example, the decrease rates of the hole mobility are 1.149 and 0.646, respectively, for DC (forward scan) and PIV methods. By using PIV method, we could obtain accurate behavior of hysteresis, hole mobility, subthreshold swing, and threshold voltage with increasing temperature. We observed notable degradation of parameter with increasing temperature. The mobility is degraded, subthreshold swing increases and threshold voltage moves to the right as temperature rises. The parameters obtained by using PIV method are accurate and will be useful in the simulation of WSe2 FETs circuit at various temperatures.
All authors have contributed to the writing of the manuscript. All authors read and approved the final manuscript.
This work was supported by the National Research Foundation of Korea (NRF-2016R1A2B3009361) and the Brain Korea 21 Plus Project in 2016.
The authors declare that they have no competing interests.
Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
- B. Radisavljevic, A. Radenovic, J. Brivio, V. Giacometti, A. Kis, Nat Nanotechnol 6, 147–150 (2011)View ArticleGoogle Scholar
- B. Radisavljevic, A. Kis, Nat Mater 12, 815–820 (2013)View ArticleGoogle Scholar
- Y. Yoon, K. Ganapathi, S. Salahuddin, Nano Lett 11, 3768–3773 (2011)View ArticleGoogle Scholar
- O. Lopez-Sanchez, D. Lembke, M. Kayci, A. Radenovic, A. Kis, Nat Nanotechnol 8, 497–501 (2013)View ArticleGoogle Scholar
- F.K. Perkins, A.L. Friedman, E. Cobas, P.M. Campbell, G.G. Jernigan, B.T. Jonker, Nano Lett 13, 668–673 (2013)View ArticleGoogle Scholar
- D.J. Late et al., ACS Nano 7, 4879–4891 (2013)View ArticleGoogle Scholar
- H. Fang, S. Chuang, T.C. Chang, K. Takei, T. Takahashi, A. Javey, Nano Lett 12, 3788–3792 (2012)View ArticleGoogle Scholar
- W. Liu, J. Kang, D. Sarkar, Y. Khatami, D. Jena, K. Banerjee, Nano Lett 13, 1983–1990 (2013)View ArticleGoogle Scholar
- W. Liu, W. Cao, J. Kang, K. Banerjee, ECS Trans 58(7), 281–285 (2013)View ArticleGoogle Scholar
- D.J. Late, B. Liu, H.R. Matte, V.P. Dravid, C.N.R. Rao, ACS Nano 6, 5635–5641 (2012)View ArticleGoogle Scholar
- W. Park, Y. G. Lee, J. J. Kim, S. K. Lee, C. G. Kang, C. Cho, and B. H. Lee, in International Conference on Solid State Device and Materials, SSDM, 2013, pp. 684–685Google Scholar
- D. Estrada, S. Dutta, A. Liao, E. Pop, Nanotechnology 21(8), 085702 (2010)View ArticleGoogle Scholar
- I. Meric, C.R. Dean, A.F. Young, N. Baklitskaya, N.J. Tremblay, C. Nuckolls, K.L. Shepard, Nano Lett 11(3), 1093–1097 (2011)View ArticleGoogle Scholar
- J.M. Park, D. Lee, J. Shim, T. Jeon, K. Eom, B.G. Park, J.H. Lee, Semicond Sci Technol 29(9), 095006 (2014)View ArticleGoogle Scholar
- Y.G. Lee et al., Appl Phys Lett 102, 093121 (2013)View ArticleGoogle Scholar
- Roh et al., Nanotechnology 26, 455201 (2015)View ArticleGoogle Scholar
- J.-M. Park, I. Tak, W. Kang, B. G. Park and J. H. Lee, in International Conference on Electronics, Information, and Communication (ICEIC), 2016, pp. 369–372Google Scholar