The proposed model is described in two sub-sections (2.1 and 2.2). Sub-section 2.1 describes a fully ballistic nanoscale SDG MOSFET model that evolves from Natori’s ballistic model. In Sub-section 2.2, the proposed model of 2.1 is modified from complete ballistic to a realistic quasi-ballistic model by considering the carrier scattering dependency near the low field source region, in terms of transmission and reflection co-efficients as per the scattering theory.

2.1. Using the concept of flux theory, the net drain to source current in a bulk nanoscale MOSFET is expressed as

$$I_{ds} = I_{ + } - I_{ - }$$

(1)

where \(I_{ + }\) is the left to right current component and \(I_{ - }\) is the right to left current component as shown in Fig. 2. \(E_{fS}\) and \(E_{fD}\) in Fig. 2 represent source and drain Fermi levels respectively. The Fermi-levels of degenerately doped source and drain are indicated with dash-dot lines. The highest energy barrier appears to be near the source, where electrons with allowed discrete sub-bands populate. Carriers confined in an inversion layer occupy discrete sub- bands with a minimum energy \(E_{j}\) above the conduction band \(E^{\prime}_{c} .\) The probability of an electronic state being filled by an electron is given by the Fermi–Dirac distribution function

$$f_{D} \left( E \right) = \frac{1}{{1 + e^{{\frac{{\left( {E - E_{f} } \right)}}{kT}}} }}$$

(2)

where the parameter \(E_{f}\) is the Fermi energy level. The energy level \(E = (E'_{c} + E_{j} + {\text{KE}})\), is represented in Fig. 2. Under equilibrium conditions \(I_{ds} = 0.\) For non-equilibrium conditions, the net drain to source current is expressed using one sub band approximation (lowest being j = 0 of unprimed valley) as

$$\begin{aligned} I_{{ds}} & = \, {\mathcal{G}}\left[ {F_{{1/2}} \left( {\frac{{E_{{fS}} - E_{c}^{\prime } - E_{0} }}{{kT}}} \right)} \right. \\ & \quad \left. - \, F_{{1/2}} \left( {\frac{{E_{{fS}} - E_{c}^{\prime } - E_{0} }}{{kT}} - \frac{{V_{{ds}} }}{{v_{T} }}} \right) \right]\\ \end{aligned}$$

(3)

where the parameter \({\mathcal{G}} = \frac{{8\sqrt {2m_{t} } qW(kT)^{3/2} }}{{h^{2} }}\) as in [12]. The Fermi–Dirac integral is then approximated as in [13] and given in (4) as

$$F_{{{\raise0.7ex\hbox{$1$} \!\mathord{\left/ {\vphantom {1 2}}\right.\kern-0pt} \!\lower0.7ex\hbox{$2$}}}} \left( {\frac{{E_{fS} - E^{\prime}_{c} - E_{0} }}{kT}} \right) \approx {\raise0.7ex\hbox{$2$} \!\mathord{\left/ {\vphantom {2 3}}\right.\kern-0pt} \!\lower0.7ex\hbox{$3$}}\left( {\frac{{E_{fS} - E^{\prime}_{c} - E_{0} }}{kT}} \right)^{{\frac{3}{2}}}$$

(4)

In (4) the expression in the bracket is given as

$$\begin{aligned} & \left( {\frac{{E_{{fS}} - E_{c}^{\prime } - E_{0} }}{{kT}}} \right) \hfill \\ & \quad = \ln \left[ {\frac{1}{2}\left\{ {\sqrt {\left( {e^{{\frac{{V_{{ds}} }}{{v_{T} }}}} - 1} \right)^{2} + 4\exp \left( g \right)} - 1 - e^{{\frac{{V_{{ds}} }}{{v_{T} }}}} } \right\}} \right] \hfill \\ \end{aligned}$$

(5)

Here, \(g\) is another intermediary parameter given as

$$g = \left( {\frac{{h^{2} \varepsilon_{ox} \left( {V_{gs} - V_{t} } \right)}}{{4\pi qkTt_{ox} m_{t} }} + \frac{{V_{ds} }}{{v_{T} }}} \right)$$

(6)

In the above equations \(h\) is the Plank’s constant, \(\varepsilon_{ox}\) is the gate oxide permittivity, \(V_{t}\) is the threshold voltage, \(t_{ox}\) is the oxide layer thickness, thermal voltage \(v_{T} = \frac{kT}{q}\) and \(m_{t} = 0.19m_{0}\) where \(m_{0}\) is the free electron mass. Substituting (5) and (6) in (4) and the resultant value in (3), the drain current for a bulk ballistic MOSFET is obtained that includes both Fermi–Dirac statistics and carrier degeneracy.

Generally, symmetrical device structures simplify the mathematical analysis and steps involved in the modelling process. Hence, the device structure considered in the proposed work is a nanoscale symmetric Double Gate MOSFET (SDG) as mentioned in Fig. 3. In SDG MOSFETs, both gates have identical work function and hence switch together giving rise to two inversion channels (one at top of silicon film and the other at the bottom). The current and inversion charge capacitances are doubled in the double gate case. However, the prime advantage is in the ability of DG MOSFETs to scale to a shorter channel length well beyond bulk CMOS limit. Due to the aforementioned reasons, the drain current for a fully ballistic symmetric DG ballistic MOSFET is obtained by multiplying (3) with a factor of two that is mathematically expressed in (7) as

$$\begin{aligned} I_{ds} & = 2{\mathcal{G}}\left[ {F_{1/2} \left( {\frac{{E_{fS} - E^{\prime}_{c} - E_{0} }}{kT}} \right)} \right. \\ & \quad \left. -\, {F_{1/2} \left( {\frac{{E_{fS} - E^{\prime}_{c} - E_{0} }}{kT} - \frac{{V_{ds} }}{{v_{T} }}} \right)} \right] \end{aligned}$$

(7)

The silicon film in Fig. 3 is assumed to be lightly doped and fully depleted so that the discrete dopant fluctuations do not arise. The threshold voltage \(V_{t}\) in (6) is determined as in [14] because it is completely dependent on the gate work function. In order to achieve lower threshold voltages, the proposed work considers n + polysilicon as gate material.

2.2. As per the ballistic transport theory, current needs to be evaluated at the top of the channel barrier. In a ballistic MOSFET, due to the ballistic injection process, velocity saturates at the top of the barrier where the electric field is zero. However, in a long channel device, velocity saturates near the drain due to scattering at the high electric field drain region. Equation (7) represents a fully ballistic DG MOSFET model that is independent of channel length when the mean free path of carriers exhibits the condition of (\(\lambda \sim L\)). The measured current values in [15] show that the modern nanoscale transistors of channel lengths in the range \(\left( {10\,{\text{nm}} < L < 100\,{\text{nm}}} \right)\) are quasi-ballistic (i.e. approximately 20% to 50% of ballistic limit in the saturation part). The lesser current observed is due to the carrier scattering dependency observed near the low field source region in the semi-ballistic regime. As the channel length is scaled towards nanoscale regime, the proposed model satisfactorily includes the scattering effects in terms of transmission and reflection coefficients. Scattering equation in a nanoscale SDG MOSFET can be expressed from the elementary scattering theory in terms of transmission coefficient \((T_{C} )\) and reflection coefficient \((R_{C} )\) in (8) as

$$T_{C} + R_{C} = 1$$

(8)

where

$$T_{C} = \frac{\lambda }{\lambda + L }\quad {\text{and}} \quad R_{C} = \frac{L}{\lambda + L }$$

(9)

To avoid complexity, the proposed work assumes elastic scattering [16] and also considers that the average velocity of backscattered carriers is equal to that of injected carriers. Based on (8) and (9) a simple relation between diffusive and ballistic transport is given further. If \(T_{C} = 0 \;{\text{and}}\;L \gg \lambda ,\) then the transport is drift-diffusive with significant scattering. Else, if \(T_{C} = 1\; {\text{and}}\;L \ll \lambda ,\) then the transport is strongly ballistic and all injected carriers enter the drain. The mean free path \(\lambda\) depends on effective mobility \(\mu_{eff}\) of electrons (Appendix: Eq. 17). The effective mobility is calculated considering 2D electrostatics as in [17, 18] as a function of transverse electric field. A nanoscale DG MOSFET consists of a low field region near the source that is firmly controlled by gate voltage \(V_{gs}\) and a high field region near the drain that is greatly controlled by drain voltage \(V_{ds}\) as shown in Fig. 4. Here, the mean free path \(\lambda\) and channel \({\text{length }}L\) are sufficient to determine transport with scattering for low drain bias. However, for high drain bias with the condition mentioned in Fig. 5, carrier scattering depends on the critical layer width \(\delta ,\) near the low field source region. Scattering near the drain has a lesser effect on backscattering to the source. Hence, it is the scattering that occurs immediately after the critical layer \(\delta\) near the source (as shown in Fig. 5) that matters for most of the transmission. This positional carrier scattering dependency near the low field small source region \(\delta\) is responsible for quasi-ballistic nature of devices. Based on the preceding intuition and considering condition for the critical layer width near source as \(\delta \ll L,\) the transmission co-efficient term in (9) is re-written by replacing *L* by \(\delta\) and expressed in (10) as

$$T_{C} = \frac{\lambda }{\lambda + \delta }$$

(10)

Finally, using (10), the drain current equation in (7) is re-written and expressed in (11) as

$$\begin{aligned} I_{ds} &= 2{\mathcal{G}}T_{C} \left[ {F_{1/2} \left( {\frac{{E_{fS} - E^{\prime}_{c} - E_{0} }}{kT}} \right)} \right. \\ & \quad \left. - \, {F_{1/2} \left( {\frac{{E_{fS} - E^{\prime}_{c} - E_{0} }}{kT} - \frac{{qV_{ds} }}{kT}} \right)} \right] \end{aligned}$$

(11)

Thus, in very short channels, due to the quasi-ballistic transport, the carriers diffuse above the threshold region (top of the barrier near the source) unlike long channel where it is the drift current during high drain bias. This small bottleneck region that is usually lesser than the mean free path of the carriers, limits the current in a nanoscale device. After the critical layer width \(\delta ,\) the ballistic transport starts to dominate. In Fig. 3 it is seen that due to the absence of body contacts, a SDG MOSFET can have only 3 terminals (with both gates tied). Let \(Q_{g} ,Q_{d} \;{\text{and}}\;Q_{s}\) be the terminal charges associated with gate, drain and source respectively for the device shown in Fig. 3. The analytical expressions for the terminal charges applicable for a long channel SDG MOSFET are given in [19]. The terminal charges in the proposed model evolve from these analytical expressions and are modified accordingly to be applicable for nanoscale device lengths considering quasi-ballistic transport. Finally, the solutions for four capacitances (that are independent of each other), are also explicitly given as

$$C_{gd} = - \frac{{L^{2} g^{2}_{ds} }}{{\mu_{eff} I_{ds} }} + \frac{{Q_{g} g_{ds} }}{{I_{ds} }}$$

(12)

$$C_{sd} = \frac{{\left( {Q_{s} - Q_{d} } \right)g_{ds} }}{{I_{ds} }}$$

(13)

$$C_{dg} = - \frac{{L^{2} g^{2}_{ds} }}{{\mu_{eff} I_{ds} }} + \frac{{Q_{g} g_{ds} }}{{I_{ds} }} - \frac{{\left( {Q_{s} - Q_{d} } \right)g_{m} }}{{I_{ds} }}$$

(14)

$$C_{gs} = \frac{{L^{2} (g^{2}_{ds} + g_{m} )^{2} }}{{\mu_{eff} I_{ds} }} + \frac{{Q_{g} (g_{ds} + g_{m} )}}{{I_{ds} }}$$

(15)

where \(g_{m}\) is the gate transconductance and \(g_{ds}\) is drain-to-source conductance. The above expressions partially evolve from [20] and are modified accordingly so as to consider both diffusive and ballistic transport phenomena. The results in the next section illustrate and discuss the completeness of the model in terms of current, charges and capacitances.