The degradation data of the key device electrical parameters extracted from Figures 4 and 5 are shown in Figure 6, and the time progression of interface trap generation during the TLP are shown as interface trap concentration (Nit) versus pulse time in Figures 7, 8 and 9. The maximum trap concentration over the entire Si-SiO2 interfaces is shown in Figure 7, and the average trap concentration level at the source/drain regions are shown in Figures 8 and 9 respectively.
From Figure 6, we can see that the on-state resistance (Ron) and off-state drain leakage (refer to right y-axis) current increase with the TLP stress level, while the transconductance (gm), threshold voltage (Vth) and saturation current decrease with the TLP stress level. Under the pulse stress at two-thirds of It2, the on-resistance nearly doubled. The saturation drain current degrades the least among all the device parameters, but the degraded off-state drain leakage current can be thousands of times of that in the degradation-free device. The physical mechanisms of the changes in these device parameters will be explained in the next section.
It is know that the GAA nanowire device has good gate controllability due to the gate stack configuration, and its off-state leakage current is much lower than other device structures [1, 5]. However, as we can see here, this advantage is lost when it is subjected to ESD stress, and hence effective ESD protection to the device is critically important to leverage on the strength of the GAA SiNW FET.
The upper bound of interface trap concentration is set as the silicon dangling bond concentration at the Si-SiO2 interface (1012 cm-2 is used in this work [17]). From Figures 7, 8 and 9, we can see that the maximum interface trap concentration increases rapidly at the rising edge of the stress pulse while the average trap concentrations increase relatively slower.
Figure 9 shows that the increase in the average trap concentration at the drain region is similar to the maximum trap concentration increase as shown in Figure 7, indicating that more interface traps are generated at the drain region at the rising stage of the stress pulse, indicating that the mechanism of interface traps generation is due to hot carrier injection instead of bias temperature instability.
After the pulse rising time, the traps increase steadily, and the trap concentration at the drain region interface is much higher than that at the source region interface. These observations will be explained in the next section.
Degradation analysis
The device performance will be severely degraded due to the reduction of carrier mobility as more scattering occur upon the trap charge formation at the Si-SiO2 interface. The degradation is expected to be more severe for the GAA nanowire device as the surface to volume ratio of nanowire body is high.
Our TLP simulation indicates that the hotspot position is in the drain extension region as shown in Figure 10, and hence the major degradation mechanism in GAA nanowire device should be at the drain junction.
Under the TLP stress condition, the increase in the interface trap charge concentration at Si-SiO2 interface enhances the carrier scattering which in turn reduces the carrier mobility and channel current, thus Ron rises and gm decreases as observed in Figure 6. The induced interface trap charge in the channel region is also responsible for the threshold voltage shifting [18]. The degraded threshold voltage means less effective gate control, which in turn increase the off-state current dramatically.
With the increase in the electrons trap concentration at the interface, the channel current path moves slightly further away from the interface as reported by Chen et al. [18, 19]. This, together with the reduction in the channel current, suppresses the impact ionization and further reduces the generation rate of interface traps due to hot carrier injection (HCI). Therefore, the interface states or degradation reaches certain equilibrium state after some time as observed in Figures 8 and 9 where the average trap concentration maintains at a level after first 50 ns stress. For low level stress, the saturation interface states level is far from the upper limit of interface states, which indicates that there is no more newly created interface traps. If the stress pulse is strong enough, as in the case of 10 mA/μm stress, the maximum interface trap concentration can reach the saturation limit as shown in Figure 7.
The impact ionization generation is nearly absent when the TLP stress level is lower than 7.5 mA/μm, which is half of the It2. Above 7.5 mA/μm stress level, impact ionization generates electron-hole pairs massively at the drain side as shown in Figure 11. The normal electric field shows a peak region at the drain extension, and it also becomes more significant when stress level is above 7.5 mA/μm as depicted in Figure 12. High electron current density and high parallel electric field as shown in Figure 13 also exist at the drain extension, which suggests that more hot electrons injection occur at this position. Therefore, the electron density at the drain side increases rapidly during the pulse rising edge due to the TLP current injection. However the electron current density at the source side does not vary as much as that at the drain side. This explains a sudden rising of interface states at the drain side, while no such effect is observed at the source side.
A large negative magnitude of normal electric field also exists at the drain to drain extension and the source to source extension as shown in Figure 12. This negative field suggests a favor for hole injection at these two positions. Trap of holes could induce negative mirror charge near the interface, increase the effective electron concentration. This mechanism results in drain current increase and Ron decrease. However such reverse shifting behavior of device electrical parameter is not observed in our simulation since the electron trap is dominating. As the intrinsic p-type doping level of nanowire is much lower than the source/drain doping, there are relatively fewer active holes as compare to electrons, thus the dominant carrier trap and degradation mechanism is hot electron injection related, and the hot hole injection is only a minor competing mechanism in this case. The time progression of electron and hole trap concentration is depicted in Figure 14. With higher stress current level, the electron trap becomes even more effective due to larger positive normal electric field and there are more accumulated electrons, and the impact of the hot hole injection is becoming less as can be seen in Figure 14. Therefore, the Ron shifting curve shown in Figure 6 shows an increasing slope with the ESD stress level.
The ESD stress seriously degrades the device performance by generating the charged interface traps, and high level charge traps could reduce the oxide breakdown voltage, and in some cases, the breakdown voltage is so low that local oxide melts due to the local conduction path formed by accumulated oxide traps. This is also reported by Tseng and Hwu [15].
From the above analysis, we can see that ESD TLP stress on the drain of GAA nanowire FET will first trigger the hot carrier injection at Si-SiO2 interface which degrades the device performance. If the stress level is high or the stress persists, oxide breakdown will occur, and in some severe cases, oxide melt will be observed. All these degradation mechanisms are indeed observed experimentally in [2].
During our simulations, the gate terminal is kept at floating. Since GAA devices is a fully depletion device, the ESD current mainly discharges through the nanowire channel, and thus their ESD robustness is strongly dependence on the gate voltage. As the gate could also couple the transient voltage from the drain terminal during TLP stress, the ESD damage should be even more significant if the gate is grounded, and this will be investigated in our future work.